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zedboard: disable soc uart for all variants (zynq does not need it, for soft cpus there are no pins)

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This commit is contained in:
Ilia Sergachev 2021-12-22 03:27:30 +01:00
parent 53ce00b3fd
commit bc3c42ab5f
1 changed files with 1 additions and 1 deletions

2
litex_boards/targets/digilent_zedboard.py
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@ -53,7 +53,6 @@ class BaseSoC(SoCCore):
if kwargs.get("cpu_type", None) == "zynq7000": if kwargs.get("cpu_type", None) == "zynq7000":
kwargs['integrated_sram_size'] = 0 kwargs['integrated_sram_size'] = 0
kwargs['with_uart'] = False
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
@ -159,6 +158,7 @@ def main():
soc_core_args(parser) soc_core_args(parser)
vivado_build_args(parser) vivado_build_args(parser)
parser.set_defaults(cpu_type="zynq7000") parser.set_defaults(cpu_type="zynq7000")
parser.set_defaults(no_uart=True)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(