targets/digilent_nexys_video: Use reset_buf on sys_clk's create_clkout to improve timings and demonstrate use.
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@ -49,7 +49,7 @@ class _CRG(LiteXModule):
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self.pll = pll = S7PLL(speedgrade=-1)
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq, reset_buf="bufg")
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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pll.create_clkout(self.cd_idelay, 200e6)
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