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targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).

This commit is contained in:
Florent Kermarrec 2020-02-28 09:46:54 +01:00
parent b44885d222
commit be5ed35871
7 changed files with 39 additions and 24 deletions
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10
litex_boards/targets/camlink_4k.py
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@ -11,6 +11,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import camlink_4k
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
@ -93,15 +95,17 @@ class BaseSoC(SoCSDRAM):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help='gateware toolchain to use, trellis (default) or diamond')
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(toolchain_path="/usr/local/diamond/3.10_x64/bin/lin64")
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
if __name__ == "__main__":
main()

5
litex_boards/targets/colorlight_5a_75b.py
View File

@ -23,6 +23,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import colorlight_5a_75b
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
@ -125,6 +127,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75B")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default) or 6.1")
parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
@ -139,7 +142,7 @@ def main():
else:
soc = BaseSoC(args.revision, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
builder.build(**trellis_argdict(args))
if __name__ == "__main__":
main()

8
litex_boards/targets/hadbadge.py
View File

@ -14,6 +14,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import hadbadge
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
@ -70,18 +72,20 @@ class BaseSoC(SoCSDRAM):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help='gateware toolchain to use, diamond or trellis (default)')
help='gateware toolchain to use, trellis (default) or diamond')
parser.add_argument("--sys-clk-freq", default=48e6,
help="system clock frequency (default=48MHz)")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
if __name__ == "__main__":
main()

9
litex_boards/targets/orangecrab.py
View File

@ -75,7 +75,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", **kwargs):
def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
platform = orangecrab.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
@ -100,8 +100,8 @@ class BaseSoC(SoCSDRAM):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help="gateware toolchain to use, diamond (default) or trellis")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
@ -111,7 +111,8 @@ def main():
soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
if __name__ == "__main__":
main()

9
litex_boards/targets/trellisboard.py
View File

@ -108,7 +108,7 @@ class EthernetSoC(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, toolchain="diamond", **kwargs):
def __init__(self, toolchain="trellis", **kwargs):
BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
@ -136,8 +136,8 @@ class EthernetSoC(BaseSoC):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help="gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
@ -150,7 +150,8 @@ def main():
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
if __name__ == "__main__":
main()

14
litex_boards/targets/ulx3s.py
View File

@ -12,6 +12,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import ulx3s
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
@ -50,7 +52,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, device="LFE5U-45F", toolchain="diamond",
def __init__(self, device="LFE5U-45F", toolchain="trellis",
sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
@ -72,16 +74,17 @@ class BaseSoC(SoCSDRAM):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help="gateware toolchain to use, trellis (default) or diamond")
parser.add_argument("--device", dest="device", default="LFE5U-45F",
help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F')
help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
parser.add_argument("--sys-clk-freq", default=50e6,
help="system clock frequency (default=50MHz)")
parser.add_argument("--sdram-module", default="MT48LC16M16",
help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(device=args.device, toolchain=args.toolchain,
@ -89,7 +92,8 @@ def main():
sdram_module_cls=args.sdram_module,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
if __name__ == "__main__":
main()

8
litex_boards/targets/versa_ecp5.py
View File

@ -130,8 +130,8 @@ class EthernetSoC(BaseSoC):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help="gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
@ -144,9 +144,7 @@ def main():
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = {}
if args.toolchain == "trellis":
builder_kargs == trellis_argdict(args)
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)
if __name__ == "__main__":