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Merge pull request #152 from gsomlo/gls-nexys4ddr-etherbone 

nexys4ddr: add etherbone support
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enjoy-digital 2021-01-16 12:02:54 +01:00 committed by GitHub
parent 6a5f2f59a6 e71a4940c0
commit bee71da774
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 12 additions and 6 deletions
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18
litex_boards/targets/nexys4ddr.py
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@ -56,7 +56,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_vga=False, **kwargs): def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_vga=False, **kwargs):
platform = nexys4ddr.Platform() platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_----------------------------------------------- # SoCCore ----------------------------------_-----------------------------------------------
@ -85,13 +85,16 @@ class BaseSoC(SoCCore):
l2_cache_reverse = True l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet: if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII( self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth")) pads = self.platform.request("eth"))
self.add_csr("ethphy") self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy) if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# VGA terminal ----------------------------------------------------------------------------- # VGA terminal -----------------------------------------------------------------------------
if with_vga: if with_vga:
@ -120,6 +123,7 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
@ -127,9 +131,11 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
**soc_sdram_argdict(args) **soc_sdram_argdict(args)
) )
assert not (args.with_spi_sdcard and args.with_sdcard) assert not (args.with_spi_sdcard and args.with_sdcard)