targets/CRG: Add rst signal when missing.
Allow properly reseting the PLL from the SoC.
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ace789653f
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@ -39,6 +39,7 @@ from litespi.opcodes import SpiNorFlashOpCodes as Codes
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, iodelay_clk_freq, with_video_pll=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys4x = ClockDomain()
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@ -54,6 +55,7 @@ class _CRG(LiteXModule):
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clk100 = platform.request("clk100")
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
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@ -66,6 +68,7 @@ class _CRG(LiteXModule):
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# Video PLL.
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if with_video_pll:
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self.video_pll = video_pll = S7MMCM(speedgrade=-1)
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self.comb += video_pll.reset.eq(self.rst)
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video_pll.register_clkin(clk100, 100e6)
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video_pll.create_clkout(self.cd_hdmi, 40e6)
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video_pll.create_clkout(self.cd_hdmi5x, 5*40e6)
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@ -27,6 +27,7 @@ from litex.soc.cores.hyperbus import HyperRAM
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys8x = ClockDomain()
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@ -35,6 +36,7 @@ class _CRG(LiteXModule):
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# # #
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
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@ -32,6 +32,7 @@ mB = 1024*kB
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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@ -48,6 +49,7 @@ class _CRG(LiteXModule):
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# PLL
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self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
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self.comb += sys_pll.reset.eq(self.rst)
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sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
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sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done)
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@ -28,12 +28,13 @@ from litepcie.software import generate_litepcie_software
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(ResetSignal("pcie"))
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self.comb += pll.reset.eq(ResetSignal("pcie") | self.rst)
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pll.register_clkin(ClockSignal("pcie"), 125e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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@ -36,6 +36,7 @@ from litepcie.software import generate_litepcie_software
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_pll4x = ClockDomain()
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@ -44,6 +45,7 @@ class _CRG(LiteXModule):
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# # #
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self.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 200e6)
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@ -29,6 +29,7 @@ mB = 1024*kB
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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@ -38,7 +39,7 @@ class _CRG(LiteXModule):
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# PLL.
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self.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk33, 33.333e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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@ -28,6 +28,7 @@ from liteeth.phy.titaniumrgmii import LiteEthPHYRGMII
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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@ -37,7 +38,7 @@ class _CRG(LiteXModule):
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# PLL
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self.pll = pll = TITANIUMPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk25, 25e6)
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# You can use CLKOUT0 only for clocks with a maximum frequency of 4x
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# (integer) of the reference clock. If all your system clocks do not fall within
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@ -27,6 +27,7 @@ from liteeth.phy.trionrgmii import LiteEthPHYRGMII
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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@ -37,7 +38,7 @@ class _CRG(LiteXModule):
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# PLL
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self.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk40, 40e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="axi_clk")
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@ -26,6 +26,7 @@ from litex.soc.cores.led import LedChaser
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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@ -35,7 +36,7 @@ class _CRG(LiteXModule):
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# PLL
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self.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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@ -24,6 +24,7 @@ from litex.soc.cores.led import LedChaser
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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@ -33,7 +34,7 @@ class _CRG(LiteXModule):
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# PLL
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self.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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@ -28,6 +28,7 @@ mB = 1024*kB
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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@ -37,7 +38,7 @@ class _CRG(LiteXModule):
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# PLL.
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self.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk33, 33.333e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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@ -45,6 +45,7 @@ from litepcie.software import generate_litepcie_software
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class CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_pcie=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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@ -57,6 +58,7 @@ class CRG(LiteXModule):
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]
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else:
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self.pll = pll = S7PLL(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk60"), 60e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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@ -32,6 +32,7 @@ mB = 1024*kB
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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# PLL.
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self.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk33, 33.333e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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@ -32,6 +32,7 @@ mB = 1024*kB
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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@ -51,6 +52,7 @@ class _CRG(LiteXModule):
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# PLL
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self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
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self.comb += sys_pll.reset.eq(self.rst)
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sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
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sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done )
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@ -25,7 +25,8 @@ from litex.soc.cores.led import LedChaser
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.cd_sys = ClockDomain()
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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rst_n = platform.request("user_btn", 0)
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self.comb += self.cd_sys.clk.eq(clk24)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n | self.rst)
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -56,7 +56,7 @@ class _CRG(LiteXModule):
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# PLL
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self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done)
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk27, 27e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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self.specials += [
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@ -46,6 +46,7 @@ from litescope import LiteScopeAnalyzer
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, ddram_channel, with_hbm):
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if with_hbm:
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_hbm_ref = ClockDomain()
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self.cd_apb = ClockDomain()
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@ -60,6 +61,7 @@ class _CRG(LiteXModule):
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if with_hbm:
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self.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hbm_ref, 100e6)
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@ -31,6 +31,7 @@ from litedram.phy import s7ddrphy
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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@ -53,7 +54,7 @@ class _CRG(LiteXModule):
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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self.comb += pll.reset.eq(~por_done)
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self.comb += pll.reset.eq(~por_done | self.rst)
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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