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efinix_ti60_f225: Add the 3 QSE connectors and add RGMII Ethernet QSE extension board.

This commit is contained in:
Florent Kermarrec 2022-06-13 16:01:28 +02:00
parent b32969c29f
commit c420429a3c
1 changed files with 41 additions and 3 deletions
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44
litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py
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@ -2,6 +2,7 @@
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
@ -125,13 +126,50 @@ iobank_info = [
("TR", "1.8 V LVCMOS"),
]
# Connectors ---------------------------------------------------------------------------------------
# QSE Connectors -----------------------------------------------------------------------------------
_connectors = [
["P1", " - H14 - G14 - - F12 G13 E12 F13 - - E15 H13 E14 H12 - - C13 G15 D13 F15",
" - - D15 G11 D14 F11 - - C14 N14 C15 P14 - - K4 A4 J3 B5"],
["P1",
#3V3 5V GND GND GND GND GND GND
"--- H14 --- G14 --- --- F12 G13 E12 F13 --- --- E15 H13 E14 H12 --- --- C13 G15",
"D13 F15 --- --- D15 G11 D14 F11 --- --- C14 N14 C15 P14 --- --- K4 A4 J3 B5",
# GND GND GND GND GND GND
],
["P2",
#3V3 5V GND GND GND GND GND GND
"--- R9 --- P9 --- --- L11 N10 K11 M10 --- --- L12 R10 L13 P10 --- --- M14 R12",
"M15 R11 --- --- K10 P11 J10 P12 --- --- K12 N13 J12 P15 --- --- H5 H4 P13 R14",
# GND GND GND GND GND GND
],
["P3",
#3V3 5V GND GND GND GND GND GND
"--- R5 --- P5 --- --- M7 R6 L7 P6 --- --- R8 N6 P8 M6 --- --- K7 R7",
" L8 P7 --- --- N8 L6 M8 K6 --- --- M9 A3 L9 B3 --- --- E10 C3 F10 C4",
# GND GND GND GND GND GND
],
]
# QSE Extensions -----------------------------------------------------------------------------------
def rgmii_ethernet_qse_ios(con):
return [
("eth_clocks", 0,
Subsignal("tx", Pins(f"{con}:26")),
Subsignal("rx", Pins(f"{con}:2")),
IOStandard("1.8_V_LVCMOS"),
),
("eth", 0,
Subsignal("rx_ctl", Pins(f"{con}27")),
Subsignal("rx_data", Pins(f"{con}:21 {con}:19 {con}:15 {con}:13")),
Subsignal("tx_ctl", Pins(f"{con}:20")),
Subsignal("tx_data", Pins(f"{con}:16 {con}:14 {con}:10 {con}:8")),
Subsignal("rst_n", Pins(f"{con}:40")),
Subsignal("mdc", Pins(f"{con}:39")),
Subsignal("mdio", Pins(f"{con}:37")),
IOStandard("1.8_V_LVCMOS"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(EfinixPlatform):