Merge pull request #180 from hansfbaier/master
Add board support for Terasic/Arrow DECA board (Intel Max10)
This commit is contained in:
enjoy-digital
GitHub
commit
c55b606faf
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@ -128,7 +128,9 @@ The Colorlight5A is a very nice board to start with, cheap, powerful, easy to us
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| C10LPRefKit | Intel Cyclone10 | 10CL055 | 50MHz | FTDI | 16-bit 32MB SDR | No | 100Mbps MII | 16MB QSPI | No |
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| C10LPRefKit | Intel Cyclone10 | 10CL055 | 50MHz | FTDI | 16-bit 32MB SDR | No | 100Mbps MII | 16MB QSPI | No |
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| De0Nano | Intel Cyclone4 | EP4CE22F | 50MHz | FTDI | 16-bit 32MB SDR | No | No | No | No |
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| De0Nano | Intel Cyclone4 | EP4CE22F | 50MHz | FTDI | 16-bit 32MB SDR | No | No | No | No |
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| De10Lite | Intel MAX10 | 10M50DA | 50MHz | IOs | 16-bit 64MB SDR | No | No | No | No |
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| De10Lite | Intel MAX10 | 10M50DA | 50MHz | IOs | 16-bit 64MB SDR | No | No | No | No |
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| DECA | Intel MAX10 | 10M50DA | 50MHz | JTAG | 16-bit 512MG DDR3* | No | Yes | No | Yes |
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| De10Nano | Intel Cyclone5 | 5CSEBA6 | 50MHz | IOs | 16-bit 32MB SDR | No | No | No | Yes |
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| De10Nano | Intel Cyclone5 | 5CSEBA6 | 50MHz | IOs | 16-bit 32MB SDR | No | No | No | Yes |
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| Arrow SoCKit | Intel Cyclone5 | 5CSXFC6D6F31C8| 50MHz | JTAG | 32-bit 1GB DDR3* | No | No | No | No |
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| De1SoC | Intel Cyclone5 | 5CSEMA5 | 50MHz | IOs | 16-bit 64MB SDR | No | ? | ? | ? |
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| De1SoC | Intel Cyclone5 | 5CSEMA5 | 50MHz | IOs | 16-bit 64MB SDR | No | ? | ? | ? |
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| De2-115 | Intel Cyclone4 | EP4CE115 | 50MHz | IOs | 16-bit 128MB SDR | No | 1Gbps GMII* | 8MB QSPI | Yes* |
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| De2-115 | Intel Cyclone4 | EP4CE115 | 50MHz | IOs | 16-bit 128MB SDR | No | 1Gbps GMII* | 8MB QSPI | Yes* |
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| ECP5-EVN | Lattice ECP5 | LFE5UM5G-85F | 50MHz | FTDI | No | No | ? | ? | ? |
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| ECP5-EVN | Lattice ECP5 | LFE5UM5G-85F | 50MHz | FTDI | No | No | ? | ? | ? |
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@ -0,0 +1,296 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2014-2019 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# power button
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("pwr_but", 0, Pins("P9:9"), IOStandard("3.3-V LVTTL")),
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# system reset
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("sys_reset_n", 0, Pins("P9:10"), IOStandard("3.3-V LVTTL")),
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# Clk
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("adc_clk_10", 0, Pins("M9"), IOStandard("2.5 V")),
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("clk1_50", 0, Pins("M8"), IOStandard("2.5 V")),
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("clk2_50", 0, Pins("P11"), IOStandard("3.3-V LVTTL")),
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# Leds
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("user_led", 0, Pins("C7"), IOStandard("1.2 V")),
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("user_led", 1, Pins("C8"), IOStandard("1.2 V")),
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("user_led", 2, Pins("A6"), IOStandard("1.2 V")),
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("user_led", 3, Pins("B7"), IOStandard("1.2 V")),
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("user_led", 4, Pins("C4"), IOStandard("1.2 V")),
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("user_led", 5, Pins("A5"), IOStandard("1.2 V")),
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("user_led", 6, Pins("B4"), IOStandard("1.2 V")),
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("user_led", 7, Pins("C5"), IOStandard("1.2 V")),
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# Button
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("key", 0, Pins("H21"), IOStandard("1.5 V SCHMITT TRIGGER")),
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("key", 1, Pins("H22"), IOStandard("1.5 V SCHMITT TRIGGER")),
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# Switches
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("sw", 0, Pins("J21"), IOStandard("1.5 V SCHMITT TRIGGER")),
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("sw", 1, Pins("J22"), IOStandard("1.5 V SCHMITT TRIGGER")),
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# I2C: CapSense Buttons
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("cap_sense_i2c", 0,
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Subsignal("sclk", Pins("AB2")),
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Subsignal("sdat", Pins("AB3")),
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IOStandard("3.3-V LVTTL")
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),
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# board temperature sensor
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("temp", 0,
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Subsignal("cs_n", Pins("PIN_AB4")),
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Subsignal("sc", Pins("PIN_AA1")),
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Subsignal("sio", Pins("PIN_Y2")),
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IOStandard("3.3-V LVTTL")
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),
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# power monitor I2C
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("pmonitor", 0,
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Subsignal("alert", Pins("Y4")),
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Subsignal("scl", Pins("Y3")),
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Subsignal("sda", Pins("Y1")),
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IOStandard("3.3-V LVTTL")
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),
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# temperature and humidity sensor I2C
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("rh_temp", 0,
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Subsignal("drdy_n", Pins("AB9")),
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Subsignal("scl", Pins("Y10")),
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Subsignal("sda", Pins("AA10")),
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IOStandard("3.3-V LVTTL")
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),
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# proximity / ambient light sensor
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("proximity_i2c", 0,
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Subsignal("scl", Pins("Y8")),
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Subsignal("sda", Pins("AA8")),
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Subsignal("int", Pins("AA9")),
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IOStandard("3.3-V LVTTL")
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),
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# Accelerometer
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("gsensor", 0,
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Subsignal("sdi", Pins("C6")),
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Subsignal("sdo", Pins("D5")),
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Subsignal("cs_n", Pins("E9")),
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Subsignal("sclk", Pins("B5")),
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Subsignal("int1", Pins("E8")),
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Subsignal("int2", Pins("D7")),
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IOStandard("1.2 V")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"E21 V20 V21 C20 Y21 J14 V18 U20",
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"Y20 W22 C22 Y22 N18 V22 W20"),
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IOStandard("SSTL-15 CLASS I"),
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),
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Subsignal("ba", Pins("D19 W19 F19"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("ras_n", Pins("D22"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("cas_n", Pins("E20"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("we_n", Pins("E22"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("dm", Pins("N19 J15"),
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IOStandard("SSTL-15 CLASS I"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION")
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),
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Subsignal("dq", Pins(
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"L20 L19 L18 M15 M18 M14 M20 N20",
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"K19 K18 J18 K20 H18 J20 H20 H19"),
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IOStandard("SSTL-15 CLASS I"),
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Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"),
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),
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Subsignal("dqs_p", Pins("L14 K14"),
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IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"),
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Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION")
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),
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Subsignal("dqs_n", Pins("L15 K15"),
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IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"),
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Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION")
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),
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Subsignal("clk_p", Pins("D18"),
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IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"),
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Misc("D5_DELAY=2")
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),
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Subsignal("clk_n", Pins("E18"),
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IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"),
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Misc("D5_DELAY=2")
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),
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Subsignal("cs_n", Pins("F22"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("cke", Pins("B22"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("odt", Pins("G22"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("reset_n", Pins("U19"), IOStandard("SSTL-15 CLASS I")),
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Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")
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),
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# Audio
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("audio", 0,
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Subsignal("bclk", Pins("R14")),
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Subsignal("reset_n", Pins("M21")),
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Subsignal("din_mfp1", Pins("P15")),
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Subsignal("dout_mfp2", Pins("P18")),
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Subsignal("gpio_mfp5", Pins("M22")),
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Subsignal("mclk", Pins("P14")),
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Subsignal("miso_mfp4", Pins("N21")),
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Subsignal("sclk_mfp3", Pins("P19")),
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Subsignal("scl_ss_n", Pins("P20")),
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Subsignal("sda_mosi", Pins("P21")),
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Subsignal("spi_select", Pins("N22")),
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Subsignal("wclk", Pins("R15")),
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IOStandard("1.5 V")
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),
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# USB ULPI
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("ulpi", 0,
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Subsignal("fault_n", Pins("D8"), IOStandard("1.2 V")),
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Subsignal("clk", Pins("H11"), IOStandard("1.2 V")),
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Subsignal("stp", Pins("J12")),
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Subsignal("dir", Pins("J13")),
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Subsignal("nxt", Pins("H12")),
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Subsignal("reset_n", Pins("E16")),
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Subsignal("data", Pins("E12 E13 H13 E14 H14 D15 E15 F15")),
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IOStandard("1.8 V")
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),
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("sdcard", 0,
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Subsignal("sel", Pins("P13"), IOStandard("3.3-V LVTTL")),
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Subsignal("fb_clk", Pins("R22")),
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Subsignal("clk", Pins("T20")),
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Subsignal("cmd", Pins("T21")),
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Subsignal("data", Pins("R18 T18 T19 R20")),
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IOStandard("1.5 V")
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),
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# MII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("T5")),
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Subsignal("rx", Pins("T6")),
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IOStandard("2.5 V"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("R3")),
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Subsignal("mdio", Pins("N8")),
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Subsignal("mdc", Pins("R5")),
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Subsignal("rx_dv", Pins("P4")),
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Subsignal("rx_er", Pins("V1")),
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Subsignal("rx_data", Pins("U5 U4 R7 P8")),
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Subsignal("tx_en", Pins("P3")),
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Subsignal("tx_data", Pins("U2 W1 N9 W2")),
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Subsignal("col", Pins("R4")),
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Subsignal("crs", Pins("P5")),
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Subsignal("pcf_en", Pins("V9"), IOStandard("3.3 V")),
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IOStandard("2.5 V"),
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),
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# HDMI
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("hdmi", 0,
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Subsignal("tx_d_r", Pins("C18 D17 C17 C19 D14 B19 D13 A19 C14")),
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Subsignal("tx_d_g", Pins("C14 A17 B16 C15 A14 A15 A12 A16")),
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Subsignal("tx_d_b", Pins("A13 C16 C12 B17 B12 B14 A18 C13")),
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Subsignal("tx_clk", Pins("A20")),
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Subsignal("tx_de", Pins("C9")),
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Subsignal("tx_hs", Pins("B11")),
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Subsignal("tx_vs", Pins("C11")),
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Subsignal("tx_int", Pins("B10")),
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Misc("FAST_OUTPUT_REGISTER ON"),
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IOStandard("1.8 V")
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),
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("hdmi_i2c", 0,
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Subsignal("scl", Pins("C10")),
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Subsignal("sda", Pins("B15")),
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IOStandard("1.8 V")
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),
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("hdmi_i2s", 0,
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Subsignal("i2s", Pins("A9 A11 A8 B8")),
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Subsignal("mclk", Pins("A7")),
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Subsignal("lrclk", Pins("A10")),
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Subsignal("sclk", Pins("D12")),
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IOStandard("3.3-V LVTTL")
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),
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# MIPI
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("camera", 0,
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Subsignal("mclk", Pins("U3")),
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Subsignal("clkp", Pins("N5")),
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Subsignal("clkn", Pins("N4")),
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Subsignal("dp", Pins("R2 N1 T2 N2")),
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Subsignal("dn", Pins("R1 P1 T1 N3")),
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Subsignal("reset_n", Pins("T3")),
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Subsignal("wp", Pins("U1")),
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Subsignal("core_en", Pins("V3")),
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IOStandard("2.5 V"),
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),
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# LP-MIPI
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("camera", 1,
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Subsignal("mclk", Pins("U3"), IOStandard("2.5 V")),
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Subsignal("clkp", Pins("E11")),
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Subsignal("clkn", Pins("E10")),
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Subsignal("dp", Pins("A4 C3 B1 B3")),
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Subsignal("dn", Pins("A3 C2 B2 A2")),
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IOStandard("1.2 V"),
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),
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("mipi_i2c", 0,
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Subsignal("scl", Pins("M1")),
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Subsignal("sda", Pins("M2")),
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IOStandard("2.5 V")
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),
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("gpio", 0, Pins("P8:3 P8:4 P8:5 P8:6 P8:7 P8:8 P8:9 P8:10",
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"P8:11 P8:12 P8:13 P8:14 P8:15 P8:16 P8:17 P8:18",
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"P8:19 P8:20 P8:21 P8:22 P8:23 P8:24 P8:25 P8:26",
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"P8:27 P8:28 P8:29 P8:30 P8:31 P8:32 P8:33 P8:34",
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"P8:35 P8:36 P8:37 P8:38 P8:39 P8:40 P8:41 P8:42",
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"P8:43 P8:44 P8:45 P8:46"),
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IOStandard("3.3-V LVTTL")
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),
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("gpio", 1, Pins("P9:11 P9:12 P9:13 P9:14 P9:15 P9:16 P9:17 P9:18",
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"P9:19 P9:20 P9:21 P9:22 P9:23 P9:24 P9:25 P9:26",
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"P9:27 P9:28 P9:29 P9:30 P9:31 P9:41 P9:42"),
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IOStandard("3.3-V LVTTL")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Beagle bone black headers (numbering 1-based, Pin 0 is dummy)
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# PIN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
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("P8", "- - - W18 Y18 Y19 AA17 AA20 AA19 AB21 AB20 AB19 Y16 V16 AB18 V15 W17 AB17 AA16 AB16 W16 AB15 W15 Y14 AA15 AB14 AA14 AB13 AA13 AB12 AA12 AB11 AA11 AB10 Y13 Y11 W13 W12 W11 V12 V11 V13 V14 Y17 W14 U15 R13"),
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||||||
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("P9", "- - - - - - - - - U6 AA2 Y5 Y6 W6 W7 W8 V8 AB8 V7 R11 AB7 AB6 AA7 AA6 Y7 V10 U7 W9 W5 R9 W4 P9 - K4 - J4 H3 J8 J9 F5 F4 V17 W3 - - - -")
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||||||
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]
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||||||
|
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||||||
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# Platform -----------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
class Platform(AlteraPlatform):
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||||||
|
default_clk_name = "clk1_50"
|
||||||
|
default_clk_period = 1e9/50e6
|
||||||
|
create_rbf = False
|
||||||
|
|
||||||
|
def __init__(self):
|
||||||
|
AlteraPlatform.__init__(self, "10M50DAF484C6GES", _io, _connectors)
|
||||||
|
# disable config pin so bank8 can use 1.2V
|
||||||
|
self.add_platform_command("set_global_assignment -name AUTO_RESTART_CONFIGURATION ON")
|
||||||
|
self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
|
||||||
|
self.add_platform_command("set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF")
|
||||||
|
|
||||||
|
def create_programmer(self):
|
||||||
|
return USBBlaster()
|
||||||
|
|
||||||
|
def do_finalize(self, fragment):
|
||||||
|
AlteraPlatform.do_finalize(self, fragment)
|
||||||
|
self.add_period_constraint(self.lookup_request("clk1_50", loose=True), 1e9/50e6)
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
#!/usr/bin/env python3
|
||||||
|
|
||||||
|
#
|
||||||
|
# This file is part of LiteX-Boards.
|
||||||
|
#
|
||||||
|
# Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
|
||||||
|
# SPDX-License-Identifier: BSD-2-Clause
|
||||||
|
|
||||||
|
import os
|
||||||
|
import argparse
|
||||||
|
|
||||||
|
from migen import *
|
||||||
|
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||||
|
|
||||||
|
from litex.build.io import DDROutput
|
||||||
|
|
||||||
|
from litex_boards.platforms import deca
|
||||||
|
|
||||||
|
from litex.soc.cores.clock import Max10PLL
|
||||||
|
from litex.soc.integration.soc import SoCRegion
|
||||||
|
from litex.soc.integration.soc_core import *
|
||||||
|
from litex.soc.integration.soc_sdram import *
|
||||||
|
from litex.soc.integration.builder import *
|
||||||
|
from litex.soc.cores.led import LedChaser
|
||||||
|
|
||||||
|
from litevideo.terminal.core import Terminal
|
||||||
|
|
||||||
|
# CRG ----------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
class _CRG(Module):
|
||||||
|
def __init__(self, platform, sys_clk_freq):
|
||||||
|
self.rst = Signal()
|
||||||
|
self.clock_domains.cd_sys = ClockDomain()
|
||||||
|
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
|
||||||
|
|
||||||
|
# # #
|
||||||
|
|
||||||
|
# Clk / Rst
|
||||||
|
clk50 = platform.request("clk1_50")
|
||||||
|
|
||||||
|
# PLL
|
||||||
|
self.submodules.pll = pll = Max10PLL(speedgrade="-6")
|
||||||
|
self.comb += pll.reset.eq(self.rst)
|
||||||
|
pll.register_clkin(clk50, 50e6)
|
||||||
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
||||||
|
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
|
||||||
|
|
||||||
|
# BaseSoC ------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
class BaseSoC(SoCCore):
|
||||||
|
def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
|
||||||
|
platform = deca.Platform()
|
||||||
|
|
||||||
|
# Defaults to UART over JTAG because no hardware uart is on the board
|
||||||
|
if kwargs["uart_name"] == "serial":
|
||||||
|
kwargs["uart_name"] = "jtag_atlantic"
|
||||||
|
|
||||||
|
# SoCCore ----------------------------------------------------------------------------------
|
||||||
|
SoCCore.__init__(self, platform, sys_clk_freq,
|
||||||
|
ident = "LiteX SoC on DECA",
|
||||||
|
ident_version = True,
|
||||||
|
**kwargs)
|
||||||
|
|
||||||
|
# CRG --------------------------------------------------------------------------------------
|
||||||
|
self.submodules.crg = _CRG(platform, sys_clk_freq)
|
||||||
|
|
||||||
|
# Leds -------------------------------------------------------------------------------------
|
||||||
|
self.submodules.leds = LedChaser(
|
||||||
|
pads = platform.request_all("user_led"),
|
||||||
|
sys_clk_freq = sys_clk_freq)
|
||||||
|
self.add_csr("leds")
|
||||||
|
|
||||||
|
# Build --------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
def main():
|
||||||
|
parser = argparse.ArgumentParser(description="LiteX SoC on DECA")
|
||||||
|
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||||
|
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||||
|
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
|
||||||
|
builder_args(parser)
|
||||||
|
soc_sdram_args(parser)
|
||||||
|
args = parser.parse_args()
|
||||||
|
|
||||||
|
soc = BaseSoC(
|
||||||
|
sys_clk_freq = int(float(args.sys_clk_freq)),
|
||||||
|
**soc_sdram_argdict(args)
|
||||||
|
)
|
||||||
|
builder = Builder(soc, **builder_argdict(args))
|
||||||
|
builder.build(run=args.build)
|
||||||
|
|
||||||
|
if args.load:
|
||||||
|
prog = soc.platform.create_programmer()
|
||||||
|
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
|
||||||
|
|
||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
||||||
|
|
@ -87,12 +87,14 @@ class TestTargets(unittest.TestCase):
|
||||||
# Intel Cyclone5
|
# Intel Cyclone5
|
||||||
platforms.append("de1soc")
|
platforms.append("de1soc")
|
||||||
platforms.append("de10nano")
|
platforms.append("de10nano")
|
||||||
|
platforms.append("arrow_sockit")
|
||||||
|
|
||||||
# Intel Cyclone10
|
# Intel Cyclone10
|
||||||
platforms.append("c10lprefkit")
|
platforms.append("c10lprefkit")
|
||||||
|
|
||||||
# Intel Max10
|
# Intel Max10
|
||||||
platforms.append("de10lite")
|
platforms.append("de10lite")
|
||||||
|
platforms.append("deca")
|
||||||
|
|
||||||
# Lattice iCE40
|
# Lattice iCE40
|
||||||
platforms.append("fomu_evt")
|
platforms.append("fomu_evt")
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue