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targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM.

This commit is contained in:
Florent Kermarrec 2024-08-28 15:53:53 +02:00
parent 4002b8167c
commit c5d1a252c5
4 changed files with 4 additions and 4 deletions
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2
litex_boards/targets/ice_v_wireless.py
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@ -134,7 +134,7 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.spram = Up5kSPRAM(size=128 * KILOBYTE)
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
self.bus.add_region("sram", SoCRegion(
origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
size = 64 * KILOBYTE,

2
litex_boards/targets/icebreaker.py
View File

@ -82,7 +82,7 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.spram = Up5kSPRAM(size=128 * KILOBYTE)
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
self.bus.add_region("sram", SoCRegion(
origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
size = 64 * KILOBYTE,

2
litex_boards/targets/icebreaker_bitsy.py
View File

@ -113,7 +113,7 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.spram = Up5kSPRAM(size=128 * KILOBYTE)
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
self.bus.add_region("sram", SoCRegion(
origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
size = 64 * KILOBYTE,

2
litex_boards/targets/kosagi_fomu.py
View File

@ -85,7 +85,7 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.spram = Up5kSPRAM(size=128 * KILOBYTE)
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
self.bus.add_region("sram", SoCRegion(
origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
size = 64 * KILOBYTE,