ocp_tap_timecard: Fix GTPE2 location.
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@ -100,6 +100,8 @@ class BaseSoC(SoCCore):
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self.add_pcie(phy=self.pcie_phy, ndmas=1, address_width=64)
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# FIXME: Apply it to all targets (integrate it in LitePCIe?).
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platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
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platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_support/*gtp_channel.gtpe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells -hierarchical -filter {{NAME=~pcie_support/*gtp_channel.gtpe2_channel_i}}]")
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# ICAP (For FPGA reload over PCIe).
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from litex.soc.cores.icap import ICAP
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