Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ocp_tap_timecard: Fix GTPE2 location.

This commit is contained in:
Florent Kermarrec 2023-01-13 11:47:52 +01:00
parent 8b0d4787c7
commit c753bf7fc1
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex_boards/targets/ocp_tap_timecard.py
View File

@ -100,6 +100,8 @@ class BaseSoC(SoCCore):
self.add_pcie(phy=self.pcie_phy, ndmas=1, address_width=64) self.add_pcie(phy=self.pcie_phy, ndmas=1, address_width=64)
# FIXME: Apply it to all targets (integrate it in LitePCIe?). # FIXME: Apply it to all targets (integrate it in LitePCIe?).
platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_support/*gtp_channel.gtpe2_channel_i}}]")
platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells -hierarchical -filter {{NAME=~pcie_support/*gtp_channel.gtpe2_channel_i}}]")
# ICAP (For FPGA reload over PCIe). # ICAP (For FPGA reload over PCIe).
from litex.soc.cores.icap import ICAP from litex.soc.cores.icap import ICAP