titanium_ti60_f225_dev_kit: Add HyperRAM separator.
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@ -66,6 +66,7 @@ class BaseSoC(SoCCore):
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q64JW(Codes.READ_1_1_1), with_master=True)
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self.add_spi_flash(mode="1x", module=W25Q64JW(Codes.READ_1_1_1), with_master=True)
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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if with_hyperram:
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7)
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024))
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024))
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