targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv).

litex_boards/targets/antmicro_datacenter_ddr4_test_board.py

@@ -118,7 +118,7 @@ class BaseSoC(SoCCore):
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
             self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE))
+            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx"))
 
         # SD Card ----------------------------------------------------------------------------------
         if with_sdcard:

litex_boards/targets/antmicro_lpddr4_test_board.py

@@ -81,7 +81,7 @@ class BaseSoC(SoCCore):
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
             self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE))
+            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx"))
 
         # SD Card ----------------------------------------------------------------------------------
         if with_sdcard:

litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py

@@ -84,7 +84,7 @@ class BaseSoC(SoCCore):
 
             # HyperRAM Bus/Slave Interface.
             hyperram_bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
-            self.bus.add_slave(name="main_ram", slave=hyperram_bus, region=SoCRegion(origin=0x40000000, size=hyperram_size))
+            self.bus.add_slave(name="main_ram", slave=hyperram_bus, region=SoCRegion(origin=0x40000000, size=hyperram_size, mode="rwx"))
 
             # HyperRAM L2 Cache.
             hyperram_cache = wishbone.Cache(

litex_boards/targets/lattice_crosslink_nx_vip.py

@@ -87,8 +87,7 @@ class BaseSoC(SoCCore):
             size = 8 * MEGABYTE
             hr_pads = platform.request("hyperram", int(hyperram))
             self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"],
-                size=size))
+            self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"], size=size, mode="rwx"))
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:

litex_boards/targets/sipeed_tang_nano_4k.py

@@ -125,7 +125,7 @@ class BaseSoC(SoCCore):
             self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
             self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk)
             self.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8 * MEGABYTE))
+            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8 * MEGABYTE, mode="rwx"))
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:

litex_boards/targets/sipeed_tang_nano_9k.py

@@ -112,7 +112,7 @@ class BaseSoC(SoCCore):
                 os.system("mv hyperbus.py.txt hyperbus.py")
             from hyperbus import HyperRAM
             self.hyperram = HyperRAM(hyperram_pads)
-            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4 * MEGABYTE))
+            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4 * MEGABYTE, mode="rwx"))
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:

litex_boards/targets/trenz_c10lprefkit.py

@@ -73,7 +73,7 @@ class BaseSoC(SoCCore):
 
         # HyperRam ---------------------------------------------------------------------------------
         self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-        self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE))
+        self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx"))
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:

litex_boards/targets/trenz_te0725.py

@@ -48,7 +48,7 @@ class BaseSoC(SoCCore):
         size = int((64 * MEGABYTE) / 8)
         hr_pads = platform.request("hyperram", 0)
         self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
-        self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size))
+        self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size, mode="rwx"))
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser: