targets/efinix: Now rely in LiteX to automatically exclude Tristate IOs.
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@ -91,9 +91,6 @@ class BaseSoC(SoCCore):
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if with_etherbone:
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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self.add_etherbone(phy=self.ethphy)
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# FIXME: Avoid this.
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").mdio)
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# Extension board on P2 + External Logic Analyzer.
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# Extension board on P2 + External Logic Analyzer.
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_pmod_ios = [
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_pmod_ios = [
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("debug", 0, Pins(
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("debug", 0, Pins(
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@ -72,7 +72,6 @@ class BaseSoC(SoCCore):
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from litespi.modules import W25Q128JV
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from litespi.modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True)
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self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True)
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platform.toolchain.excluded_ios.append(platform.lookup_request("spiflash4x").dq)
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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if with_led_chaser:
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@ -99,8 +98,6 @@ class BaseSoC(SoCCore):
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clock_pads = platform.request("eth_clocks", eth_phy),
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clock_pads = platform.request("eth_clocks", eth_phy),
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pads = platform.request("eth", eth_phy),
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pads = platform.request("eth", eth_phy),
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with_hw_init_reset = False)
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with_hw_init_reset = False)
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# FIXME: Avoid this.
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").mdio)
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# Use Ethernet RMII PMOD.
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# Use Ethernet RMII PMOD.
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else:
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else:
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from litex.build.generic_platform import Pins, Subsignal, IOStandard
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from litex.build.generic_platform import Pins, Subsignal, IOStandard
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