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targets/kcu105: create specific cd_eth for ethphy.

This commit is contained in:
Florent Kermarrec 2020-09-24 10:25:55 +02:00
parent 5b7288cfee
commit cc53206aff
1 changed files with 3 additions and 1 deletions
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4
litex_boards/targets/kcu105.py
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@ -32,6 +32,7 @@ class _CRG(Module):
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # # # # #
@ -40,6 +41,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk125"), 125e6) pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_clk200, 200e6, with_reset=False) pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
pll.create_clkout(self.cd_eth, 200e6)
self.specials += [ self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div", Instance("BUFGCE_DIV", name="main_bufgce_div",
@ -87,7 +89,7 @@ class BaseSoC(SoCCore):
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone: if with_ethernet or with_etherbone:
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
data_pads = self.platform.request("sfp", 0), data_pads = self.platform.request("sfp", 0),
sys_clk_freq = self.clk_freq) sys_clk_freq = self.clk_freq)
self.add_csr("ethphy") self.add_csr("ethphy")