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targets/uartbone: Update with LiteX change.

This commit is contained in:
Florent Kermarrec 2023-07-20 15:42:47 +02:00
parent 72a951081a
commit ce121663ff
6 changed files with 6 additions and 6 deletions
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2
litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
View File

@ -141,7 +141,7 @@ class BaseSoC(SoCCore):
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone("serial", baudrate=1e6)
self.add_uartbone(baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:

2
litex_boards/targets/antmicro_lpddr4_test_board.py
View File

@ -108,7 +108,7 @@ class BaseSoC(SoCCore):
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone("serial", baudrate=1e6)
self.add_uartbone(baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:

2
litex_boards/targets/colorlight_5a_75x.py
View File

@ -196,7 +196,7 @@ class BaseSoC(SoCCore):
if with_uartbone:
if board != "i5a-907":
raise ValueError("uartbone only supported on i5a-907")
self.add_uartbone(name="uartbone")
self.add_uartbone(uart_name="uartbone")
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:

2
litex_boards/targets/lattice_ice40up5k_evn.py
View File

@ -98,7 +98,7 @@ class BaseSoC(SoCCore):
# Add a UARTBone bridge --------------------------------------------------------------------
debug_uart = False
if debug_uart:
self.add_uartbone(name="serial")
self.add_uartbone()
# Flash --------------------------------------------------------------------------------------------

2
litex_boards/targets/mnt_rkx7.py
View File

@ -183,7 +183,7 @@ class BaseSoC(SoCCore):
# LiteScope Analyzer -----------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
self.add_uartbone(name="debug_serial")
self.add_uartbone(uart_name="debug_serial")
analyzer_signals = [
ulpi_data.din,
utmi.linestate,

2
litex_boards/targets/terasic_deca.py
View File

@ -86,7 +86,7 @@ class BaseSoC(SoCCore):
# UARTbone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone(name=real_uart_name, baudrate=kwargs["uart_baudrate"])
self.add_uartbone(uart_name=real_uart_name, baudrate=kwargs["uart_baudrate"])
# JTAGbone ---------------------------------------------------------------------------------
if with_jtagbone: