Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/Ultrascale+: use USPDDRPHY.

This commit is contained in:
Florent Kermarrec 2020-03-10 16:05:59 +01:00
parent ce922613a7
commit cf58550bba
3 changed files with 11 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
litex_boards/targets/mercury_xu5.py
View File

@ -84,12 +84,11 @@ class BaseSoC(SoCSDRAM):
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sim_device = "ULTRASCALE_PLUS",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6,
cmd_latency = 0,
sys_clk_freq = sys_clk_freq)
cmd_latency = 0)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
sdram_module = MT40A256M16(sys_clk_freq, "1:4")

9
litex_boards/targets/vcu118.py
View File

@ -86,10 +86,11 @@ class BaseSoC(SoCSDRAM):
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
sim_device = "ULTRASCALE_PLUS")
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6,
cmd_latency = 0)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
sdram_module = EDY4016A(sys_clk_freq, "1:4")

7
litex_boards/targets/zcu104.py
View File

@ -85,12 +85,11 @@ class BaseSoC(SoCSDRAM):
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram_32"), # FIXME: use ddram_64
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram_32"), # FIXME: use ddram_64
memtype = "DDR4",
sim_device = "ULTRASCALE_PLUS",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
cmd_latency = 1,
sys_clk_freq = sys_clk_freq)
cmd_latency = 1)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
sdram_module = KVR21SE15S84(sys_clk_freq, "1:4")