Merge branch 'litex-hub:master' into master
This commit is contained in:
Guilherme Salustiano
GitHub
commit
d0d90e9eef
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@ -80,22 +80,45 @@ _usb_uart_pmod_io = [
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_connectors = [
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("pmoda", "N15 L14 K16 K14 N16 L15 J16 J14"), # XADC
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("pmodb", "T20 U20 V20 W20 Y18 Y19 W18 W19"),
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("pmodb", "V8 W8 U7 V7 Y7 Y6 V6 W6"),
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("pmodc", "V15 W15 T11 T10 W14 Y14 T12 U12"),
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("pmodd", "T14 T15 P14 R14 U14 U15 V17 V18"),
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("pmode", "V12 W16 J15 H15 V13 U17 T17 Y17"),
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]
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ps7_config = {
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"z7-20" : {
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"PCW_UIPARAM_DDR_PARTNO" : "MT41K256M16 RE-125",
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"PCW_FPGA_FCLK0_ENABLE" : "1",
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"PCW_UART1_BAUD_RATE" : "115200",
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"PCW_EN_UART1" : "1",
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"PCW_UART1_PERIPHERAL_ENABLE" : "1",
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"PCW_UART1_UART1_IO" : "MIO 48 .. 49",
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"PCW_PRESET_BANK1_VOLTAGE" : "LVCMOS 1.8V",
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"PCW_USE_M_AXI_GP0" : "1",
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"PCW_USE_S_AXI_GP0" : "1",
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"PCW_USB0_PERIPHERAL_ENABLE" : "1",
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"PCW_USB0_USB0_IO" : "MIO 28 .. 39",
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"PCW_USB0_RESET_ENABLE" : "1",
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"PCW_USB0_RESET_IO" : "MIO 46",
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"PCW_EN_USB0" : "1"
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}
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}
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain=toolchain)
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def __init__(self, variant="z7-20", toolchain="vivado"):
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device = {
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"z7-10": "xc7z010-clg400-1",
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"z7-20": "xc7z020-clg400-1"
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}[variant]
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Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.add_extension(_ps7_io)
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self.add_extension(_usb_uart_pmod_io)
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self.ps7_config = ps7_config[variant]
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def create_programmer(self):
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return VivadoProgrammer()
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@ -19,23 +19,23 @@ from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.cores import cpu
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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assert sys_clk_freq == 100e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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@ -43,32 +43,79 @@ class _CRG(LiteXModule):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
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def __init__(self, sys_clk_freq=100e6, variant="z7-10", with_ps7=False, with_led_chaser=True, **kwargs):
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platform = digilent_zybo_z7.Platform()
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self.builder = None
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000")
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self.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB.
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if kwargs.get("cpu_type", None) == "zynq7000":
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kwargs["integrated_sram_size"] = 0x0
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kwargs["with_uart"] = False
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self.mem_map = {
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'csr': 0x4000_0000, # Zynq GP0 default
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}
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zybo Z7", **kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
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os.system("wget https://github.com/litex-hub/litex-boards/files/8339591/zybo_z7_ps7.txt)")
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os.makedirs("xci", exist_ok=True)
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os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
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self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
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self.cpu.use_rom = True
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if variant == "z7-10":
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository? Make config
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os.makedirs("xci", exist_ok=True)
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os.system("wget https://github.com/litex-hub/litex-boards/files/8339591/zybo_z7_ps7.txt")
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os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
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self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
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else:
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self.cpu.set_ps7(name="ps", config = platform.ps7_config)
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# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
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# Connect AXI GP0 to the SoC with base address of 0x40000000 (default one)
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = 0x43c00000)
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base_address = 0x40000000)
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self.bus.add_master(master=wb_gp0)
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#TODO memory size dependend on board variant
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self.bus.add_region("sram", SoCRegion(
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origin = self.cpu.mem_map["sram"],
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size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"])
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)
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self.bus.add_region("rom", SoCRegion(
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origin = self.cpu.mem_map["rom"],
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size = 256 * 1024 * 1024 // 8,
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linker = True)
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)
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self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
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self.bus.add_region("flash", SoCRegion(
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origin = 0xFC00_0000,
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size = 0x4_0000,
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mode = "rwx")
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)
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# PS7 as Slave Integration ---------------------------------------------------------------------
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elif with_ps7:
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if variant == "z7-20":
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cpu_cls = cpu.CPUS["zynq7000"]
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zynq = cpu_cls(self.platform, "standard") # zynq7000 has no variants
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zynq.set_ps7(name="ps", config = platform.ps7_config)
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axi_gp_slave0 = zynq.add_axi_gp_slave(clock_domain = self.crg.cd_sys.name)
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self.submodules += zynq
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self.bus.add_slave(
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name="ps",slave=axi_gp_slave0,
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region=SoCRegion(
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origin=0x2000_0000,
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size=0x2000_0000,
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mode="rwx"
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)
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)
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else:
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#TODO: make config for zybo-z7-10
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raise NotImplementedError
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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@ -76,22 +123,72 @@ class BaseSoC(SoCCore):
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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def finalize(self, *args, **kwargs):
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super(BaseSoC, self).finalize(*args, **kwargs)
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if self.cpu_type != "zynq7000":
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return
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libxil_path = os.path.join(self.builder.software_dir, 'libxil')
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os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
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lib = os.path.join(libxil_path, 'embeddedsw')
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if not os.path.exists(lib):
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os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
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os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
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for header in [
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'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
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'lib/bsp/standalone/src/common/xil_types.h',
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'lib/bsp/standalone/src/common/xil_assert.h',
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'lib/bsp/standalone/src/common/xil_io.h',
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'lib/bsp/standalone/src/common/xil_printf.h',
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'lib/bsp/standalone/src/common/xstatus.h',
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'lib/bsp/standalone/src/common/xdebug.h',
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'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
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'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
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'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
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'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
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'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
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'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
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'lib/bsp/standalone/src/arm/common/xil_exception.h',
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'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
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]:
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shutil.copy(os.path.join(lib, header), self.builder.include_dir)
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write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
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'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
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write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
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#ifndef __XPARAMETERS_H
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#define __XPARAMETERS_H
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#include "xparameters_ps.h"
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#define STDOUT_BASEADDRESS XPS_UART1_BASEADDR
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#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
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#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
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#endif
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''')
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=digilent_zybo_z7.Platform, description="LiteX SoC on Zybo Z7.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser = LiteXArgumentParser(platform=digilent_zybo_z7.Platform, description="LiteX SoC on Zybo Z7")
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parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).")
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parser.add_target_argument("--with-ps7", action="store_true", help="Add the PS7 as slave for soft CPUs.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict
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variant = args.variant,
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with_ps7 = args.with_ps7,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **parser.builder_argdict)
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builder = Builder(soc, **builder_argdict(args))
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if args.cpu_type == "zynq7000":
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soc.builder = builder
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builder.add_software_package('libxil')
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builder.add_software_library('libxil')
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
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