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litex_acorn_baseboard_mini: WiP GTPE2_common sharing.

This commit is contained in:
Florent Kermarrec 2024-06-13 18:28:12 +02:00
parent 1b22061e93
commit d0e1c6fd37
1 changed files with 5 additions and 3 deletions
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8
litex_boards/targets/litex_acorn_baseboard_mini.py
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@ -136,13 +136,15 @@ class BaseSoC(SoCCore):
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
assert not with_sata and (not with_ethernet or with_etherbone)
#assert not with_sata and (not with_ethernet or with_etherbone)
self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1_baseboard"),
data_width = 64,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]")
platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]")
#platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]")
#platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]")
platform.toolchain.pre_placement_commands.append("remove_cell [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtpe2_common_i}}]")
# Ethernet / SATA RefClk/Shared-QPLL -------------------------------------------------------