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prog: use different openocd config files for FT232/FT2232.

This commit is contained in:
Florent Kermarrec 2020-05-06 16:14:51 +02:00
parent 117d1a1c75
commit d34c3baf15
20 changed files with 44 additions and 16 deletions
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2
litex_boards/platforms/ac701.py
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@ -223,7 +223,7 @@ class Platform(XilinxPlatform):
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/acorn_cle_215.py
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@ -93,7 +93,7 @@ class Platform(XilinxPlatform):
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/aller.py
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@ -119,7 +119,7 @@ class Platform(XilinxPlatform):
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/arty.py
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@ -259,7 +259,7 @@ class Platform(XilinxPlatform):
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi)
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/arty_s7.py
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@ -212,7 +212,7 @@ class Platform(XilinxPlatform):
def create_programmer(self):
bscan_spi = "bscan_spi_xc7s50.bit" if "xc7s50" in self.device else "bscan_spi_xc7a25.bit"
return OpenOCD("openocd_xilinx.cfg", bscan_spi)
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/genesys2.py
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@ -117,7 +117,7 @@ class Platform(XilinxPlatform):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/kc705.py
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@ -549,7 +549,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/kx2.py
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@ -73,7 +73,7 @@ class Platform(XilinxPlatform):
XilinxPlatform.__init__(self, " xc7k160tffg676-2", _io, toolchain="vivado")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7k160t.bit")
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/linsn_rv901t.py
View File

@ -293,7 +293,7 @@ class Platform(XilinxPlatform):
XilinxPlatform.__init__(self, "xc6slx16-2-ftg256", _io, _connectors)
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc6.cfg", "bscan_spi_xc6slx16.bit")
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx16.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/mimas_a7.py
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@ -183,7 +183,7 @@ class Platform(XilinxPlatform):
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a50t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a50t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/nereid.py
View File

@ -403,7 +403,7 @@ set_property CONFIG_VOLTAGE 3.3 [current_design]
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7k160t.bit")
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/nexys4ddr.py
View File

@ -132,7 +132,7 @@ class Platform(XilinxPlatform):
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/nexys_video.py
View File

@ -232,7 +232,7 @@ class Platform(XilinxPlatform):
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/sp605.py
View File

@ -167,7 +167,7 @@ class Platform(XilinxPlatform):
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc6.cfg", "bscan_spi_xc6slx45.bit")
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx45.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/tagus.py
View File

@ -168,7 +168,7 @@ class Platform(XilinxPlatform):
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex_boards/platforms/vc707.py
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@ -644,7 +644,7 @@ class Platform(XilinxPlatform):
self.add_platform_command("""set_property CONFIG_VOLTAGE 2.5 [current_design]""")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "xc7vx485t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "xc7vx485t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

0
litex_boards/prog/openocd_xilinx_xc6.cfg → litex_boards/prog/openocd_xc6_ft2232.cfg
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14
litex_boards/prog/openocd_xc6_ft232.cfg Normal file
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@ -0,0 +1,14 @@
interface ftdi
ftdi_vid_pid 0x0403 0x6014
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
reset_config none
source [find cpld/xilinx-xc6.cfg]
source [find cpld/jtagspi.cfg]
adapter_khz 25000
proc fpga_program {} {
global _CHIPNAME
xc6_program $_CHIPNAME.tap
}

0
litex_boards/prog/openocd_xilinx_xc7.cfg → litex_boards/prog/openocd_xc7_ft2232.cfg
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14
litex_boards/prog/openocd_xc7_ft232.cfg Normal file
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@ -0,0 +1,14 @@
interface ftdi
ftdi_vid_pid 0x0403 0x6014
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
reset_config none
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
adapter_khz 25000
proc fpga_program {} {
global _CHIPNAME
xc7_program $_CHIPNAME.tap
}