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sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules.

This commit is contained in:
Florent Kermarrec 2022-09-07 12:06:22 +02:00
parent 1663ded641
commit d39d87b701
2 changed files with 9 additions and 12 deletions
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14
litex_boards/platforms/sipeed_tang_primer_20k.py
View File

@ -50,8 +50,7 @@ _io = [
IOStandard("LVCMOS33"), IOStandard("LVCMOS33"),
), ),
# DDR3 SDRAM IMD128M16R39CG8GNF-125 # DDR3 SDRAM IMD128M16R39CG8GNF-125.
# DQ group L cannot work now
("ddram", 0, ("ddram", 0,
Subsignal("a", Pins("F7 A4 D6 F8 C4 E6 B1 D8 A5 F9 K3 B7 A3 C8"), Subsignal("a", Pins("F7 A4 D6 F8 C4 E6 B1 D8 A5 F9 K3 B7 A3 C8"),
IOStandard("SSTL15")), IOStandard("SSTL15")),
@ -60,17 +59,14 @@ _io = [
Subsignal("cas_n", Pins("R6"), IOStandard("SSTL15")), Subsignal("cas_n", Pins("R6"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("L2"), IOStandard("SSTL15")), Subsignal("we_n", Pins("L2"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("P5"), IOStandard("SSTL15")), Subsignal("cs_n", Pins("P5"), IOStandard("SSTL15")),
Subsignal("dm", Pins("K5"), IOStandard("SSTL15")), Subsignal("dm", Pins("G1 K5"), IOStandard("SSTL15")),
#Subsignal("dm", Pins("G1 K5"), IOStandard("SSTL15")),
Subsignal("dq", Pins( Subsignal("dq", Pins(
#"G5 F5 F4 F3 E2 C1 E1 B3", "G5 F5 F4 F3 E2 C1 E1 B3",
"M3 K4 N2 L1 P4 H3 R1 M2"), "M3 K4 N2 L1 P4 H3 R1 M2"),
IOStandard("SSTL15"), IOStandard("SSTL15"),
Misc("VREF=INTERNAL")), Misc("VREF=INTERNAL")),
#Subsignal("dqs_p", Pins("G2 J5"), IOStandard("SSTL15D")), Subsignal("dqs_p", Pins("G2 J5"), IOStandard("SSTL15D")),
Subsignal("dqs_p", Pins("J5"), IOStandard("SSTL15D")), Subsignal("dqs_n", Pins("G3 K6"), IOStandard("SSTL15D")),
#Subsignal("dqs_n", Pins("G3 K6"), IOStandard("SSTL15D")),
Subsignal("dqs_n", Pins("K6"), IOStandard("SSTL15D")),
Subsignal("clk_p", Pins("J1"), IOStandard("SSTL15D")), Subsignal("clk_p", Pins("J1"), IOStandard("SSTL15D")),
Subsignal("clk_n", Pins("J3"), IOStandard("SSTL15D")), Subsignal("clk_n", Pins("J3"), IOStandard("SSTL15D")),
Subsignal("cke", Pins("J2"), IOStandard("SSTL15")), Subsignal("cke", Pins("J2"), IOStandard("SSTL15")),

7
litex_boards/targets/sipeed_tang_primer_20k.py
View File

@ -22,7 +22,7 @@ from liteeth.phy.rmii import LiteEthPHYRMII
from litex_boards.platforms import sipeed_tang_primer_20k from litex_boards.platforms import sipeed_tang_primer_20k
from liteeth.phy.rmii import LiteEthPHYRMII from litedram.common import PHYPadsReducer
from litedram.modules import MT41J128M16 from litedram.modules import MT41J128M16
from litedram.phy import GW2DDRPHY from litedram.phy import GW2DDRPHY
@ -122,8 +122,9 @@ class BaseSoC(SoCCore):
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.ddrphy = GW2DDRPHY( self.submodules.ddrphy = GW2DDRPHY(
platform.request("ddram"), pads = PHYPadsReducer(platform.request("ddram"), [0, 1]),
sys_clk_freq=sys_clk_freq) sys_clk_freq = sys_clk_freq
)
self.ddrphy.settings.rtt_nom = "disabled" self.ddrphy.settings.rtt_nom = "disabled"
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)