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platforms/nexys4*: Update part name 

Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
This commit is contained in:
Shawn Anastasio 2022-10-21 14:15:27 -05:00
parent 99888c52ce
commit d4b2461b5a
2 changed files with 2 additions and 2 deletions
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2
litex_boards/platforms/digilent_nexys4.py
View File

@ -220,7 +220,7 @@ class Platform(XilinxPlatform):
default_clk_period = 1e9/100e6 default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado"): def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain) XilinxPlatform.__init__(self, "xc7a100tcsg324-1", _io, _connectors, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self): def create_programmer(self):

2
litex_boards/platforms/digilent_nexys4ddr.py
View File

@ -183,7 +183,7 @@ class Platform(XilinxPlatform):
default_clk_period = 1e9/100e6 default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado"): def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain) XilinxPlatform.__init__(self, "xc7a100tcsg324-1", _io, _connectors, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.900 [get_iobanks 34]") self.add_platform_command("set_property INTERNAL_VREF 0.900 [get_iobanks 34]")
def create_programmer(self): def create_programmer(self):