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Update qmtech_artix7_fgg676.py

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Chandler Klüser 2023-09-01 04:53:07 -03:00 committed by GitHub
parent 8b0c5b78ee
commit d8b006568a
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1 changed files with 7 additions and 1 deletions
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litex_boards/platforms/qmtech_artix7_fgg676.py
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@ -160,6 +160,12 @@ class Platform(Xilinx7SeriesPlatform):
io += daughterboard.io io += daughterboard.io
connectors += daughterboard.connectors connectors += daughterboard.connectors
if with_rp2040_daughterboard:
from litex_boards.platforms.qmtech_rp2040_daughterboard import QMTechDaughterboard
daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33"))
io += daughterboard.io
connectors += daughterboard.connectors
Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain) Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \ self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
@ -179,4 +185,4 @@ class Platform(Xilinx7SeriesPlatform):
def do_finalize(self, fragment): def do_finalize(self, fragment):
Xilinx7SeriesPlatform.do_finalize(self, fragment) Xilinx7SeriesPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)