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Merge pull request #474 from Quiddle11/master 

Avoid undefined clocks in generated sdc file
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enjoy-digital 2023-02-11 08:41:17 +01:00 committed by GitHub
parent b8abdf1b39 a354f04143
commit d8d757eec4
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1 changed files with 2 additions and 2 deletions
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litex_boards/platforms/terasic_deca.py
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@ -325,5 +325,5 @@ class Platform(AlteraPlatform):
AlteraPlatform.do_finalize(self, fragment) AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
# Generate PLL clocsk in STA # Generate PLL clocsk in STA
self.toolchain.additional_sdc_commands.append("derive_pll_clocks -create_base_clocks -use_net_name") self.toolchain.additional_sdc_commands.insert(0, "derive_pll_clocks -create_base_clocks -use_net_name")
self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty") self.toolchain.additional_sdc_commands.insert(0, "derive_clock_uncertainty")