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platforms/targets: keep in sync with LiteX

This commit is contained in:
Florent Kermarrec 2020-02-27 11:06:53 +01:00
parent 18f65a7f9d
commit d8de4fbdfb
2 changed files with 39 additions and 4 deletions
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36
litex_boards/platforms/netv2.py
View File

@ -71,6 +71,37 @@ _io = [
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
), ),
# pcie
("pcie_x1", 0,
Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("F10")),
Subsignal("clk_n", Pins("E10")),
Subsignal("rx_p", Pins("D11")),
Subsignal("rx_n", Pins("C11")),
Subsignal("tx_p", Pins("D5")),
Subsignal("tx_n", Pins("C5"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("F10")),
Subsignal("clk_n", Pins("E10")),
Subsignal("rx_p", Pins("D11 B10")),
Subsignal("rx_n", Pins("C11 A10")),
Subsignal("tx_p", Pins("D5 B6")),
Subsignal("tx_n", Pins("C5 A6"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("F10")),
Subsignal("clk_n", Pins("E10")),
Subsignal("rx_p", Pins("D11 B10 D9 B8")),
Subsignal("rx_n", Pins("C11 A10 C9 A8")),
Subsignal("tx_p", Pins("D5 B6 D7 B4")),
Subsignal("tx_n", Pins("C5 A6 C7 A4"))
),
# ethernet # ethernet
("eth_clocks", 0, ("eth_clocks", 0,
Subsignal("ref_clk", Pins("D17")), Subsignal("ref_clk", Pins("D17")),
@ -156,5 +187,6 @@ class Platform(XilinxPlatform):
default_clk_name = "clk50" default_clk_name = "clk50"
default_clk_period = 1e9/50e6 default_clk_period = 1e9/50e6
def __init__(self): def __init__(self, device="xc7a35t"):
XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado") assert device in ["xc7a35t", "xc7a100t"]
XilinxPlatform.__init__(self, device + "-fgg484-2", _io, toolchain="vivado")

7
litex_boards/targets/arty.py
View File

@ -148,8 +148,11 @@ def main():
args = parser.parse_args() args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone) assert not (args.with_ethernet and args.with_etherbone)
cls = EthernetSoC if args.with_ethernet else BaseSoC cls = BaseSoC
cls = EtherboneSoC if args.with_etherbone else BaseSoC if args.with_ethernet:
cls = EthernetSoC
if args.with_etherbone:
cls = EtherboneSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args)) builder.build(**vivado_build_argdict(args))