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targets/l2_cache_reverse: Now defaulting to False in LiteX, so setting it to False for correct Framebuffer operations is no longer required.
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parent
834125e978
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d92a2b82fb
3 changed files with 10 additions and 13 deletions
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@ -115,8 +115,7 @@ class BaseSoC(SoCCore):
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phy = self.sdrphy,
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phy = self.sdrphy,
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module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
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module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
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size = 0x40000000,
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_size = kwargs.get("l2_size", 8192)
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l2_cache_reverse = False
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)
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)
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# Video ------------------------------------------------------------------------------------
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# Video ------------------------------------------------------------------------------------
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@ -88,8 +88,7 @@ class BaseSoC(SoCCore):
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self.add_sdram("sdram",
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self.add_sdram("sdram",
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phy = self.sdrphy,
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phy = self.sdrphy,
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module = AS4C16M16(sys_clk_freq, sdram_rate),
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module = AS4C16M16(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_size = kwargs.get("l2_size", 8192)
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l2_cache_reverse = False
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)
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)
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# Video ------------------------------------------------------------------------------------
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# Video ------------------------------------------------------------------------------------
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@ -90,8 +90,7 @@ class BaseSoC(SoCCore):
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self.add_sdram("sdram",
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self.add_sdram("sdram",
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phy = self.ddrphy,
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phy = self.ddrphy,
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module = MT41K64M16(sys_clk_freq, "1:4"),
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module = MT41K64M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_size = kwargs.get("l2_size", 8192)
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l2_cache_reverse = False,
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)
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)
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# Etherbone --------------------------------------------------------------------------------
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# Etherbone --------------------------------------------------------------------------------
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