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targets/l2_cache_reverse: Now defaulting to False in LiteX, so setting it to False for correct Framebuffer operations is no longer required.

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This commit is contained in:
Florent Kermarrec 2022-01-18 11:37:55 +01:00
parent 834125e978
commit d92a2b82fb
3 changed files with 10 additions and 13 deletions
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3
litex_boards/targets/radiona_ulx3s.py
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@ -115,8 +115,7 @@ class BaseSoC(SoCCore):
phy = self.sdrphy,
module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
size = 0x40000000,
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_reverse = False
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Video ------------------------------------------------------------------------------------

3
litex_boards/targets/scarabhardware_minispartan6.py
View file

@ -88,8 +88,7 @@ class BaseSoC(SoCCore):
self.add_sdram("sdram",
phy = self.sdrphy,
module = AS4C16M16(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_reverse = False
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Video ------------------------------------------------------------------------------------

3
litex_boards/targets/siglent_sds1104xe.py
View file

@ -90,8 +90,7 @@ class BaseSoC(SoCCore):
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_reverse = False,
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Etherbone --------------------------------------------------------------------------------