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targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.

This commit is contained in:
Florent Kermarrec 2020-05-05 16:32:10 +02:00
parent b58b9b9e6a
commit da61aabc5b
7 changed files with 8 additions and 9 deletions
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3
litex_boards/targets/genesys2.py
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@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

1
litex_boards/targets/kcu105.py
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@ -68,7 +68,6 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6,
cmd_latency = 1) cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"), module = EDY4016A(sys_clk_freq, "1:4"),

3
litex_boards/targets/kx2.py
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@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/mercury_xu5.py
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@ -65,9 +65,8 @@ class BaseSoC(SoCCore):
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
cmd_latency = 0) cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT40A256M16(sys_clk_freq, "1:4"), module = MT40A256M16(sys_clk_freq, "1:4"),

3
litex_boards/targets/vc707.py
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@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/vcu118.py
View File

@ -65,9 +65,8 @@ class BaseSoC(SoCCore):
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
cmd_latency = 0) cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"), module = EDY4016A(sys_clk_freq, "1:4"),

1
litex_boards/targets/zcu104.py
View File

@ -66,7 +66,6 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
cmd_latency = 1) cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MTA4ATF51264HZ(sys_clk_freq, "1:4"), module = MTA4ATF51264HZ(sys_clk_freq, "1:4"),