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siglent_sds1104xe: Switch back to native DRAM width (now possible with Nax).

This commit is contained in:
Florent Kermarrec 2022-02-18 11:47:08 +01:00
parent d85f88f42a
commit df36cdbcc9
1 changed files with 1 additions and 1 deletions
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2
litex_boards/targets/siglent_sds1104xe.py
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@ -84,7 +84,7 @@ class BaseSoC(SoCCore):
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1]), # FIXME: Reduce to 16-bit for use with NaxRiscv.
pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)