targets/digilent_arty_z7: add flash region

2022-10-13 19:48:41 +02:00 · 2022-10-13 19:48:41 +02:00 · e44e63f65d
parent 3b339ba9a3
commit e44e63f65d
1 changed files with 1 additions and 0 deletions
--- a/litex_boards/targets/digilent_arty_z7.py
+++ b/litex_boards/targets/digilent_arty_z7.py
@ -84,6 +84,7 @@ class BaseSoC(SoCCore):
                wishbone     = wb_gp0,
                base_address = self.mem_map["csr"])
            self.bus.add_master(master=wb_gp0)
+            self.bus.add_region("flash",  SoCRegion(origin=0xFC00_0000, size=0x4_0000, mode="rwx"))

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser: