ti60_f225_dev_kit: Update to new HyperRAM core with 2:1 ratio.
Tested at up to 250MHz sys_clk -> 125MHz HyperRAM Clk.
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@ -27,8 +27,10 @@ from liteeth.phy.titaniumrgmii import LiteEthPHYRGMII
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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# # #
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@ -43,8 +45,9 @@ class _CRG(LiteXModule):
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# (integer) of the reference clock. If all your system clocks do not fall within
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# this range, you should dedicate one unused clock for CLKOUT0.
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pll.create_clkout(None, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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pll.create_clkout(self.cd_sys, sys_clk_freq, phase=0, with_reset=True)
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pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq, phase=0, with_reset=True)
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pll.create_clkout(self.cd_sys2x_ps, 2 * sys_clk_freq, phase=315, with_reset=True)
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -93,7 +96,14 @@ class BaseSoC(SoCCore):
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self.add_config("L2_SIZE", hyperram_cache_size)
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# HyperRAM Core.
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self.hyperram = HyperRAM(platform.request("hyperram"), latency=7, latency_mode="variable", sys_clk_freq=sys_clk_freq)
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self.hyperram = HyperRAM(
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pads = platform.request("hyperram"),
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latency = 7,
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latency_mode = "variable",
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sys_clk_freq = sys_clk_freq,
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clk_ratio = "2:1",
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dq_i_cd = "sys2x_ps",
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)
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self.comb += self.hyperram_cache.slave.connect(self.hyperram.bus)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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