add optional OLED peripheral to ULX3S target
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parent
929e55d7e6
commit
eba70377b7
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@ -100,6 +100,17 @@ _io = [
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Subsignal("pullup", Pins("B12 C12")),
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Subsignal("pullup", Pins("B12 C12")),
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IOStandard("LVCMOS33")
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IOStandard("LVCMOS33")
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),
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),
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("oled_spi", 0,
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Subsignal("clk", Pins("P4")),
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Subsignal("mosi", Pins("P3")),
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IOStandard("LVCMOS33"),
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),
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("oled_ctl", 0,
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Subsignal("dc", Pins("P1")),
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Subsignal("resn", Pins("P2")),
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Subsignal("csn", Pins("N2")),
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IOStandard("LVCMOS33"),
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),
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]
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]
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# Platform -----------------------------------------------------------------------------------------
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# Platform -----------------------------------------------------------------------------------------
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@ -22,6 +22,8 @@ from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.spi import SPIMaster
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from litex.soc.cores.gpio import GPIOOut
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from litedram import modules as litedram_modules
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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@ -109,6 +111,20 @@ class BaseSoC(SoCCore):
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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self.add_csr("leds")
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def add_oled(self):
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pads = self.platform.request("oled_spi")
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pads.miso = Signal()
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oled = SPIMaster(pads, 8, self.sys_clk_freq, 8e6)
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oled.add_clk_divider()
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self.submodules.oled_spi = oled
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self.add_csr("oled_spi")
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ctl_pads = self.platform.request("oled_ctl")
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oled_ctl = GPIOOut(ctl_pads)
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self.submodules.oled_ctl = oled_ctl
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self.add_csr("oled_ctl")
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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@ -121,6 +137,7 @@ def main():
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parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
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parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--with-oled", action="store_true", help="Enable SDD1331 OLED support")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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@ -137,6 +154,9 @@ def main():
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soc.add_spi_sdcard()
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soc.add_spi_sdcard()
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if args.with_sdcard:
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if args.with_sdcard:
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soc.add_sdcard()
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soc.add_sdcard()
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if args.with_oled:
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soc.add_oled()
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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builder.build(**builder_kargs, run=args.build)
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