sipeed_tang_mega_138k: new board
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng
parent
3903cdee92
commit
ebfb9b8e01
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.gowin.programmer import GowinProgrammer
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk50", 0, Pins("P16"), IOStandard("LVCMOS33")),
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("rst", 0, Pins("U4"), IOStandard("LVCMOS15")),
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# Serial.
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("serial", 0,
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Subsignal("rx", Pins("P15")),
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Subsignal("tx", Pins("N16")),
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IOStandard("LVCMOS33")
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),
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# Leds
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("led_n", 0, Pins("J14"), IOStandard("LVCMOS33")),
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("led_n", 1, Pins("R26"), IOStandard("LVCMOS33")),
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("led_n", 2, Pins("L20"), IOStandard("LVCMOS33")),
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("led_n", 3, Pins("M25"), IOStandard("LVCMOS33")),
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("led_n", 4, Pins("N21"), IOStandard("LVCMOS33")),
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("led_n", 5, Pins("N23"), IOStandard("LVCMOS33")),
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# RGMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("H24")),
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Subsignal("rx", Pins("C23")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("E17")),
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Subsignal("mdio", Pins("K22")),
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Subsignal("mdc", Pins("K23")),
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Subsignal("rx_ctl", Pins("C22")),
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Subsignal("rx_data", Pins("B26 C26 D26 E26")),
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Subsignal("tx_ctl", Pins("J24")),
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Subsignal("tx_data", Pins("K21 J21 L19 K18")),
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IOStandard("LVCMOS33"),
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),
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("ephy_clk", 0, Pins("E18"), IOStandard("LVCMOS33")),
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("sdram_clock", 0, Pins("AC26"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V17 U15 V16 U16 T23 T25 R25 P25",
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"W23 V23 W21 U24 U25")),
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Subsignal("dq", Pins(
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"V22 U22 W19 V19 Y20 W20 V26 U26",
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"AB25 AB26 AA25 AA24 Y26 Y25 W26 W25")),
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Subsignal("ba", Pins("P21 Y21")),
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Subsignal("cas_n", Pins("P24")),
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Subsignal("cs_n", Pins("U14")),
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Subsignal("ras_n", Pins("P23")),
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Subsignal("we_n", Pins("R23")),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# TODO
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk27"
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default_clk_period = 1e9/27e6
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def __init__(self, dock="standard", toolchain="gowin"):
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GowinPlatform.__init__(self, "GW5AST-LV138FPG676AES", _io, _connectors, toolchain=toolchain, devicename="GW5AST-138B")
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self.toolchain.options["use_sspi_as_gpio"] = 1
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self.toolchain.options["use_cpu_as_gpio"] = 1
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self.toolchain.options["rw_check_on_ram"] = 1
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self.toolchain.options["bit_security"] = 0
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self.toolchain.options["bit_encrypt"] = 0
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self.toolchain.options["bit_compress"] = 0
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def create_programmer(self, kit="openfpgaloader"):
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return OpenFPGALoader(cable="ft2232")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,178 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.soc.cores.clock.gowin_gw5a import GW5APLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser, WS2812
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from liteeth.phy.gw5rgmii import LiteEthPHYRGMII
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from litedram.modules import AS4C32M16
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.build.io import DDROutput
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from litex_boards.platforms import sipeed_tang_mega_138k
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_sdram=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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if with_sdram:
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self.cd_sys_ps = ClockDomain()
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# Clk
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self.clk50 = platform.request("clk50")
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rst = platform.request("rst")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(self.clk50)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done | self.rst | rst)
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pll.register_clkin(self.clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if with_sdram:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
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if with_sdram:
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sdram_clk = ClockSignal("sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=50e6,
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with_ethernet = True,
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with_etherbone = False,
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local_ip = "192.168.1.50",
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remote_ip = "",
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eth_dynamic_ip = False,
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with_sdram = False,
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with_led_chaser = True,
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with_rgb_led = False,
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with_buttons = True,
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**kwargs):
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platform = sipeed_tang_mega_138k.Platform(toolchain="gowin")
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_sdram=with_sdram)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Mega 138K", **kwargs)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("led_n"),
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sys_clk_freq = sys_clk_freq
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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tx_delay = 2e-9,
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rx_delay = 2e-9)
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self.clk50_half = Signal()
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self.specials += Instance("CLKDIV",
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p_DIV_MODE = "2",
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i_HCLKIN = self.crg.clk50,
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i_RESETN = 1,
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i_CALIB = 0,
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o_CLKOUT = self.clk50_half)
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self.specials += DDROutput(1, 0, platform.request("ephy_clk"), self.clk50_half)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, data_width=32, software_debug=True)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, data_width=32)
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if local_ip:
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local_ip = local_ip.split(".")
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self.add_constant("LOCALIP1", int(local_ip[0]))
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self.add_constant("LOCALIP2", int(local_ip[1]))
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self.add_constant("LOCALIP3", int(local_ip[2]))
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self.add_constant("LOCALIP4", int(local_ip[3]))
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if remote_ip:
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remote_ip = remote_ip.split(".")
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self.add_constant("REMOTEIP1", int(remote_ip[0]))
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self.add_constant("REMOTEIP2", int(remote_ip[1]))
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self.add_constant("REMOTEIP3", int(remote_ip[2]))
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self.add_constant("REMOTEIP4", int(remote_ip[3]))
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# SDR SDRAM --------------------------------------------------------------------------------
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if with_sdram and not self.integrated_main_ram_size:
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self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = AS4C32M16(sys_clk_freq, "1:1"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sipeed_tang_mega_138k.Platform, description="LiteX SoC on Tang Mega 138K.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
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parser.add_target_argument("--local-ip", default="192.168.1.50", help="Local IP address.")
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_sdram = args.with_sdram,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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local_ip = args.local_ip,
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remote_ip = args.remote_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs"), external=True)
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if __name__ == "__main__":
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main()
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