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Correct DDR4 IO Banks of Xilinx Alveo U200

This commit is contained in:
Do Viet Thanh 2023-02-14 06:40:12 +07:00
parent 3b36e576ba
commit ec7a5c4c0b
1 changed files with 7 additions and 7 deletions
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14
litex_boards/platforms/xilinx_alveo_u200.py
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@ -349,18 +349,18 @@ class Platform(Xilinx7SeriesPlatform):
# Reduce programming time
self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
# DDR4 memory channel C1 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 61]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 62]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 63]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 40]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 41]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 42]")
# DDR4 memory channel C2 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 67]")
# DDR4 memory channel C3 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 69]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 47]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 48]")
# DDR4 memory channel C4 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]")
# DDR4 memory channel C4 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 72]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 73]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 74]")