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qmtech-boards: fix serial so that it gets replaced by daughterboard serial correctly

This commit is contained in:
Hans Baier 2021-11-06 06:49:25 +07:00
parent 6e7c76b71e
commit ee5638a96b
3 changed files with 23 additions and 24 deletions
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16
litex_boards/platforms/qmtech_10cl006.py
View File

@ -18,13 +18,6 @@ _io = [
("key", 0, Pins("F3"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("J6"), IOStandard("3.3-V LVTTL")),
# Serial
("serial", 0,
# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
),
# SPIFlash (W25Q64)
("spiflash", 0,
# clk
@ -128,7 +121,14 @@ _connectors = [
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
core_resources = [ ("user_led", 0, Pins("L9"), IOStandard("3.3-V LVTTL")) ]
core_resources = [
("user_led", 0, Pins("L9"), IOStandard("3.3-V LVTTL")),
("serial", 0,
# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
),
]
def __init__(self, with_daughterboard=False):
device = "10CL006YU256C8G"

16
litex_boards/platforms/qmtech_5cefa2.py
View File

@ -18,12 +18,6 @@ _io = [
("key", 0, Pins("AB13"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("V18"), IOStandard("3.3-V LVTTL")),
# Serial
("serial", 0,
Subsignal("tx", Pins("J3:8"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("J3:7"), IOStandard("3.3-V LVTTL"))
),
# SPIFlash (MT25QL128ABA)
("spiflash", 0,
# clk
@ -127,7 +121,13 @@ _connectors = [
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
core_resources = [ ("user_led", 0, Pins("D17"), IOStandard("3.3-V LVTTL")) ]
core_resources = [
("user_led", 0, Pins("D17"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("J3:8"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("J3:7"), IOStandard("3.3-V LVTTL"))
),
]
def __init__(self, with_daughterboard=False):
device = "5CEFA2F23C8"
@ -145,7 +145,7 @@ class Platform(AlteraPlatform):
AlteraPlatform.__init__(self, device, io, connectors)
if with_daughterboard:
# an ethernet pin takes the config pin, so make it available
# ethernet takes the config pin, so make it available
self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
# Generate PLL clock in STA

15
litex_boards/platforms/qmtech_ep4ce15.py
View File

@ -19,13 +19,6 @@ _io = [
("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")),
# Serial
("serial", 0,
# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
),
# SPIFlash (W25Q64)
("spiflash", 0,
# clk
@ -129,7 +122,13 @@ _connectors = [
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
core_resources = [ ("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")) ]
core_resources = [
("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))
),
]
def __init__(self, with_daughterboard=False):
device = "EP4CE15F23C8"