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Merge pull request #519 from josuah/fix_crosslink_nx_uartbone 

Crosslink-NX EVN: fix UARTBone always disabled
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enjoy-digital 2023-08-28 16:31:29 +02:00 committed by GitHub
parent 5799c35247 3c0b6956cc
commit efb76133be
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1 changed files with 6 additions and 3 deletions
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litex_boards/targets/lattice_crosslink_nx_evn.py
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@ -21,6 +21,7 @@ from litex.build.generic_platform import *
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
@ -68,6 +69,7 @@ class BaseSoC(SoCCore):
} }
def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant", def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant",
with_led_chaser = True, with_led_chaser = True,
with_uartbone = False,
**kwargs): **kwargs):
platform = lattice_crosslink_nx_evn.Platform(device=device, toolchain=toolchain) platform = lattice_crosslink_nx_evn.Platform(device=device, toolchain=toolchain)
@ -84,7 +86,7 @@ class BaseSoC(SoCCore):
# 128KB LRAM (used as SRAM) --------------------------------------------------------------- # 128KB LRAM (used as SRAM) ---------------------------------------------------------------
size = 128*kB size = 128*kB
self.spram = NXLRAM(32, size) self.spram = NXLRAM(32, size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size) self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=size))
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser:
@ -93,8 +95,7 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
# UARTBone --------------------------------------------------------------------------------- # UARTBone ---------------------------------------------------------------------------------
debug_uart = False if with_uartbone:
if debug_uart:
self.add_uartbone() self.add_uartbone()
@ -109,12 +110,14 @@ def main():
parser.add_target_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).") parser.add_target_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
parser.add_target_argument("--address", default=0x0, help="Flash address to program bitstream at.") parser.add_target_argument("--address", default=0x0, help="Flash address to program bitstream at.")
parser.add_target_argument("--prog-target", default="direct", help="Programming Target (direct or flash).") parser.add_target_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
parser.add_target_argument("--with-uartbone", action="store_true", help="Add UartBone on 1st serial.")
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq, sys_clk_freq = args.sys_clk_freq,
device = args.device, device = args.device,
toolchain = args.toolchain, toolchain = args.toolchain,
with_uartbone = args.with_uartbone,
**parser.soc_argdict **parser.soc_argdict
) )
builder = Builder(soc, **parser.builder_argdict) builder = Builder(soc, **parser.builder_argdict)