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litex-boards
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global: Use new WaitTimer integrated cast to int.

This commit is contained in:
Florent Kermarrec 2023-08-01 14:56:35 +02:00
parent f780b5faed
commit efc15a91a9
2 changed files with 3 additions and 3 deletions
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2
litex_boards/platforms/qmtech_daughterboard.py
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@ -39,7 +39,7 @@ class SevenSeg(Module, AutoCSR):
self.comb += Case(hexa, cases) self.comb += Case(hexa, cases)
timer = WaitTimer(int(period*sys_clk_freq/(2*n))) timer = WaitTimer(period*sys_clk_freq/(2*n))
self.submodules += timer self.submodules += timer
self.comb += timer.wait.eq(~timer.done) self.comb += timer.wait.eq(~timer.done)
self.sync += If(timer.done, self.sync += If(timer.done,

4
litex_boards/targets/gsd_orangecrab.py
View File

@ -65,7 +65,7 @@ class _CRG(LiteXModule):
usb_pll.create_clkout(self.cd_usb_12, 12e6) usb_pll.create_clkout(self.cd_usb_12, 12e6)
# FPGA Reset (press usr_btn for 1 second to fallback to bootloader) # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
reset_timer = WaitTimer(int(48e6)) reset_timer = WaitTimer(48e6)
reset_timer = ClockDomainsRenamer("por")(reset_timer) reset_timer = ClockDomainsRenamer("por")(reset_timer)
self.submodules += reset_timer self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n) self.comb += reset_timer.wait.eq(~rst_n)
@ -135,7 +135,7 @@ class _CRGSDRAM(LiteXModule):
usb_pll.create_clkout(self.cd_usb_12, 12e6) usb_pll.create_clkout(self.cd_usb_12, 12e6)
# FPGA Reset (press usr_btn for 1 second to fallback to bootloader) # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
reset_timer = WaitTimer(int(48e6)) reset_timer = WaitTimer(48e6)
reset_timer = ClockDomainsRenamer("por")(reset_timer) reset_timer = ClockDomainsRenamer("por")(reset_timer)
self.submodules += reset_timer self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n) self.comb += reset_timer.wait.eq(~rst_n)