target: targets: add crg and begin getting it working
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross
Piotr Esden-Tempski
parent
ce9b67e2ee
commit
f0dd31f6c8
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@ -20,108 +20,56 @@ from litex.soc.integration.doc import AutoDoc
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from litex_boards.partner.platforms.icebreaker import Platform
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from litex.soc.cores.uart import UARTWishboneBridge
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import litex.soc.cores.cpu
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import os, shutil, subprocess
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoDoc):
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"""Fomu Clock Resource Generator
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Fomu is a USB device, which means it must have a 12 MHz clock. Valentyusb
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oversamples the clock by 4x, which drives the requirement for a 48 MHz clock.
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The ICE40UP5k is a relatively low speed grade of FPGA that is incapable of
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running the entire design at 48 MHz, so the majority of the logic is placed
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in the 12 MHz domain while only critical USB logic is placed in the fast
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48 MHz domain.
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Fomu has a 48 MHz crystal on it, which provides the raw clock input. This
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signal is fed through the ICE40 PLL in order to divide it down into a 12 MHz
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signal and keep the clocks within 1ns of phase. Earlier designs used a simple
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flop, however this proved unreliable when the FPGA became very full.
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"""Icebreaker Clock Resource Generator
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The following clock domains are available on this design:
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+---------+------------+---------------------------------+
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| Name | Frequency | Description |
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+=========+============+=================================+
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| usb_48 | 48 MHz | Raw USB signals and pulse logic |
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+---------+------------+---------------------------------+
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| usb_12 | 12 MHz | USB control logic |
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| clk_12 | 12 MHz | Main control logic |
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+---------+------------+---------------------------------+
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| sys | 12 MHz | System CPU and wishbone bus |
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+---------+------------+---------------------------------+
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"""
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def __init__(self, platform):
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pass
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# clk12 = platform.request("clk12")
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# clk12 = Signal()
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clk12 = platform.request("clk12")
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# reset_delay = Signal(12, reset=4095)
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# self.clock_domains.cd_por = ClockDomain()
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# self.reset = Signal()
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reset_delay = Signal(12, reset=4095)
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self.clock_domains.cd_por = ClockDomain()
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self.reset = Signal()
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# self.clock_domains.cd_sys = ClockDomain()
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# self.clock_domains.cd_usb_12 = ClockDomain()
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# self.clock_domains.cd_usb_48 = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_clk_12 = ClockDomain()
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# platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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# platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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# platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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# platform.add_period_constraint(clk48_raw, 1e9/48e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_clk_12.clk, 1e9/12e6)
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# # POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# # reset.
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# self.comb += [
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# self.cd_por.clk.eq(self.cd_sys.clk),
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# self.cd_sys.rst.eq(reset_delay != 0),
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# self.cd_usb_12.rst.eq(reset_delay != 0),
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# ]
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_clk_12.rst.eq(reset_delay != 0),
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]
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# # POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# # reset.
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# self.comb += [
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# self.cd_usb_48.rst.eq(reset_delay != 0),
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# ]
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_clk_12.clk.eq(clk12)
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# self.comb += self.cd_usb_48.clk.eq(clk48_raw)
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# self.specials += Instance(
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# "SB_PLL40_CORE",
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# # Parameters
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# p_DIVR = 0,
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# p_DIVF = 15,
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# p_DIVQ = 5,
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# p_FILTER_RANGE = 1,
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# p_FEEDBACK_PATH = "SIMPLE",
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# p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
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# p_FDA_FEEDBACK = 15,
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# p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
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# p_FDA_RELATIVE = 0,
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# p_SHIFTREG_DIV_MODE = 1,
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# p_PLLOUT_SELECT = "GENCLK_HALF",
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# p_ENABLE_ICEGATE = 0,
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# # IO
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# i_REFERENCECLK = clk48_raw,
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# o_PLLOUTCORE = clk12,
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# # o_PLLOUTGLOBAL = clk12,
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# #i_EXTFEEDBACK,
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# #i_DYNAMICDELAY,
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# #o_LOCK,
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# i_BYPASS = 0,
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# i_RESETB = 1,
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# #i_LATCHINPUTVALUE,
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# #o_SDO,
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# #i_SDI,
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# )
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# self.comb += self.cd_sys.clk.eq(clk12)
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# self.comb += self.cd_usb_12.clk.eq(clk12)
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# self.sync.por += \
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# If(reset_delay != 0,
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# reset_delay.eq(reset_delay - 1)
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# )
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# self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1)
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)
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -129,24 +77,6 @@ class _CRG(Module, AutoDoc):
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class BaseSoC(SoCCore):
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"""A SoC on iCEBreaker, optionally with a softcore CPU"""
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# Create a default CSR map to prevent values from getting reassigned.
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# This increases consistency across litex versions.
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SoCCore.csr_map = {
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"ctrl": 0, # provided by default (optional)
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"crg": 1, # user
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"uart_phy": 2, # provided by default (optional)
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"uart": 3, # provided by default (optional)
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"identifier_mem": 4, # provided by default (optional)
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"timer0": 5, # provided by default (optional)
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"cpu_or_bridge": 8,
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"usb": 9,
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"picorvspi": 10,
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"touch": 11,
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"reboot": 12,
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"rgb": 13,
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"version": 14,
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}
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# Statically-define the memory map, to prevent it from shifting across
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# various litex versions.
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SoCCore.mem_map = {
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@ -157,8 +87,7 @@ class BaseSoC(SoCCore):
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"csr": 0xe0000000, # (default shadow @0x60000000)
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}
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def __init__(self,
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pnr_placer="heap", pnr_seed=0, usb_core="dummyusb", usb_bridge=False,
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def __init__(self, pnr_placer="heap", pnr_seed=0, debug=True,
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**kwargs):
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"""Create a basic SoC for iCEBraker.
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@ -178,7 +107,11 @@ class BaseSoC(SoCCore):
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clk_freq = int(12e6)
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# Force the SRAM size to 0, because we add our own SRAM with SPRAM
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kwargs["integrated_sram_size"] = 0
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if debug:
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kwargs["uart_name"] = "crossover"
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SoCCore.__init__(self, platform, clk_freq,
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with_uart=True,
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with_ctrl=True,
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@ -192,6 +125,12 @@ class BaseSoC(SoCCore):
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
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if debug:
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self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
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self.add_wb_master(self.uart_bridge.wishbone)
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if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
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# Override default LiteX's yosys/build templates
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assert hasattr(platform.toolchain, "yosys_template")
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assert hasattr(platform.toolchain, "build_template")
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@ -229,12 +168,6 @@ class BaseSoC(SoCCore):
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# Build --------------------------------------------------------------------------------------------
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def add_dfu_suffix(fn):
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fn_base, _ext = os.path.splitext(fn)
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fn_dfu = fn_base + '.dfu'
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shutil.copyfile(fn, fn_dfu)
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subprocess.check_call(['dfu-suffix', '--pid', '1209', '--vid', '5bf0', '--add', fn_dfu])
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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@ -244,10 +177,19 @@ def main():
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parser.add_argument(
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"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
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)
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parser.add_argument(
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"--cpu", action="store_true", help="Add a CPU to the build"
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)
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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kwargs = builder_argdict(args)
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if args.cpu:
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kwargs["cpu_type"] = "vexriscv"
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kwargs["cpu_variant"]="min"
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soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed,
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debug=True, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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