Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer. 

Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
This commit is contained in:
Florent Kermarrec 2020-05-27 08:49:41 +02:00
parent d6518c7dc2
commit f19bc36813
2 changed files with 15 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
litex_boards/platforms/pano_logic_g2.py
View File

@ -9,6 +9,7 @@
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
@ -33,7 +34,7 @@ _io = [
), ),
# serial # serial
("serial", 0, # dvi ("serial", 1, # dvi
Subsignal("tx", Pins("C14")), Subsignal("tx", Pins("C14")),
Subsignal("rx", Pins("C17")), Subsignal("rx", Pins("C17")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
@ -109,7 +110,12 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125" default_clk_name = "clk125"
default_clk_period = 1e9/125e6 default_clk_period = 1e9/125e6
def __init__(self, programmer="impact", device="xc6slx150"): def __init__(self, revision="c"):
XilinxPlatform.__init__(self, "xc6slx150-2-fgg484", _io) assert revision in ["b", "c"]
device = {"b": "xc6slx150-2-fgg484", "c": "xc6slx100-2-fgg484"}[revision]
XilinxPlatform.__init__(self, device, _io)
self.add_platform_command("""CONFIG VCCAUX="2.5";""") self.add_platform_command("""CONFIG VCCAUX="2.5";""")
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
def create_programmer(self):
return OpenOCD("openocd_xc6_ft232.cfg")

11
litex_boards/targets/pano_logic_g2.py
View File

@ -35,8 +35,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), **kwargs): def __init__(self, revision, sys_clk_freq=int(50e6), **kwargs):
platform = pano_logic_g2.Platform() platform = pano_logic_g2.Platform(revision=revision)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
@ -54,13 +54,14 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2") parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revision", default="c", help="Board revision c (default) or b")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(**soc_core_argdict(args)) soc = BaseSoC(revision=args.revision, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)