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xilinx_alveo_u250: Fix.

This commit is contained in:
Florent Kermarrec 2022-11-06 22:16:11 +01:00
parent 6edfb2ca7a
commit f1e24046fd
1 changed files with 1 additions and 1 deletions
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2
litex_boards/targets/xilinx_alveo_u250.py
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@ -102,7 +102,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.argument_parser import LiteXArgumentParser
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=xilinx_alveo_u250.Platform, description="LiteX SoC on Alveo U250")
parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")