targets: Import all from litex.gen on all targets.

litex_boards/targets/adi_adrv2crr_fmc.py

@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import adi_adrv2crr_fmc
 

litex_boards/targets/adi_plutosdr.py

@@ -13,7 +13,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import adi_plutosdr
 

litex_boards/targets/alchitry_au.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import alchitry_au
 

litex_boards/targets/alchitry_mojo.py

@@ -41,7 +41,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 from litex_boards.platforms import alchitry_mojo

litex_boards/targets/aliexpress_xc7k420t.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import aliexpress_xc7k420t
 

litex_boards/targets/alinx_ax7010.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import alinx_ax7010
 

litex_boards/targets/alinx_axu2cga.py

@@ -20,7 +20,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import alinx_axu2cga
 

litex_boards/targets/antmicro_artix_dc_scm.py

@@ -12,7 +12,7 @@ import math
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import antmicro_artix_dc_scm
 

litex_boards/targets/antmicro_datacenter_ddr4_test_board.py

@@ -11,7 +11,7 @@ import json
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import antmicro_datacenter_ddr4_test_board
 

litex_boards/targets/antmicro_lpddr4_test_board.py

@@ -7,7 +7,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import antmicro_lpddr4_test_board
 

litex_boards/targets/antmicro_sdi_mipi_video_converter.py

@@ -11,7 +11,7 @@ import os
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import antmicro_sdi_mipi_video_converter
 

litex_boards/targets/arduino_mkrvidor4000.py

@@ -10,7 +10,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import arduino_mkrvidor4000
 

litex_boards/targets/avnet_aesku40.py

@@ -11,7 +11,7 @@ import os
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import avnet_aesku40
 

litex_boards/targets/berkeleylab_marble.py

@@ -26,7 +26,7 @@ then test and benchmark the etherbone link:
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import berkeleylab_marble
 

litex_boards/targets/camlink_4k.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import camlink_4k
 

litex_boards/targets/colorlight_5a_75x.py

@@ -43,7 +43,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/colorlight_i5.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/decklink_intensity_pro_4k.py

@@ -12,7 +12,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import decklink_intensity_pro_4k
 

litex_boards/targets/decklink_mini_4k.py

@@ -14,7 +14,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import decklink_mini_4k
 

litex_boards/targets/decklink_quad_hdmi_recorder.py

@@ -17,7 +17,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import decklink_quad_hdmi_recorder
 

litex_boards/targets/digilent_arty.py

@@ -14,7 +14,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_arty
 

litex_boards/targets/digilent_arty_s7.py

@@ -9,7 +9,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_arty_s7
 

litex_boards/targets/digilent_arty_z7.py

@@ -28,7 +28,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_arty_z7
 from litex.build import tools

litex_boards/targets/digilent_atlys.py

@@ -15,7 +15,7 @@ from fractions import Fraction
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_atlys
 

litex_boards/targets/digilent_basys3.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_basys3
 

litex_boards/targets/digilent_cmod_a7.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import CRG
 

litex_boards/targets/digilent_genesys2.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_genesys2
 

litex_boards/targets/digilent_nexys4.py

@@ -10,7 +10,7 @@ import math
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import CRG
 

litex_boards/targets/digilent_nexys4ddr.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_nexys4ddr
 

litex_boards/targets/digilent_nexys_video.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_nexys_video
 

litex_boards/targets/digilent_pynq_z1.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_pynq_z1
 

litex_boards/targets/digilent_zedboard.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import digilent_zedboard
 from litex.build.tools import write_to_file

litex_boards/targets/ebaz4205.py

@@ -9,7 +9,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import ebaz4205
 

litex_boards/targets/efinix_t8f81_dev_kit.py

@@ -12,7 +12,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import efinix_t8f81_dev_kit
 

litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import efinix_titanium_ti60_f225_dev_kit
 

litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py

@@ -10,7 +10,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import efinix_trion_t120_bga576_dev_kit
 

litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py

@@ -11,7 +11,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import efinix_trion_t20_bga256_dev_kit
 

litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import efinix_trion_t20_mipi_dev_kit
 

litex_boards/targets/efinix_xyloni_dev_kit.py

@@ -11,7 +11,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import efinix_xyloni_dev_kit
 

litex_boards/targets/ego1.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import ego1
 

litex_boards/targets/enclustra_mercury_kx2.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import enclustra_mercury_kx2
 

litex_boards/targets/enclustra_mercury_xu5.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import enclustra_mercury_xu5
 

litex_boards/targets/fairwaves_xtrx.py

@@ -27,7 +27,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import fairwaves_xtrx
 

litex_boards/targets/fpc_iii.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import fpc_iii
 

litex_boards/targets/fpgawars_alhambra2.py

@@ -10,7 +10,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import fpgawars_alhambra2
 

litex_boards/targets/gadgetfactory_papilio_pro.py

@@ -10,7 +10,7 @@ import argparse
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/gsd_butterstick.py

@@ -15,7 +15,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import gsd_butterstick
 

litex_boards/targets/gsd_orangecrab.py

@@ -13,7 +13,7 @@ from migen import *
 from migen.genlib.misc import WaitTimer
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import gsd_orangecrab
 

litex_boards/targets/hackaday_hadbadge.py

@@ -12,7 +12,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/ice_v_wireless.py

@@ -17,7 +17,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import ice_v_wireless
 

litex_boards/targets/icebreaker.py

@@ -20,7 +20,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import icebreaker
 

litex_boards/targets/icebreaker_bitsy.py

@@ -19,7 +19,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import icebreaker_bitsy
 

litex_boards/targets/isx_im1283.py

@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import isx_im1283
 

litex_boards/targets/jungle_electronics_fireant.py

@@ -12,7 +12,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import jungle_electronics_fireant
 

litex_boards/targets/kosagi_fomu.py

@@ -14,7 +14,7 @@ import sys
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import kosagi_fomu_pvt
 

litex_boards/targets/kosagi_netv2.py

@@ -10,7 +10,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import kosagi_netv2
 

litex_boards/targets/krtkl_snickerdoodle.py

@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import krtkl_snickerdoodle
 

litex_boards/targets/lambdaconcept_ecpix5.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import lambdaconcept_ecpix5
 

litex_boards/targets/lattice_crosslink_nx_evn.py

@@ -10,7 +10,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import lattice_crosslink_nx_evn
 

litex_boards/targets/lattice_crosslink_nx_vip.py

@@ -12,7 +12,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import lattice_crosslink_nx_vip
 

litex_boards/targets/lattice_ecp5_evn.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import lattice_ecp5_evn
 

litex_boards/targets/lattice_ecp5_vip.py

@@ -10,7 +10,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import lattice_ecp5_vip
 

litex_boards/targets/lattice_ice40up5k_evn.py

@@ -11,7 +11,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import lattice_ice40up5k_evn
 from litex.build.lattice.programmer import IceStormProgrammer

litex_boards/targets/lattice_versa_ecp5.py

@@ -10,7 +10,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import lattice_versa_ecp5
 

litex_boards/targets/limesdr_mini_v2.py

@@ -13,7 +13,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import limesdr_mini_v2
 

litex_boards/targets/linsn_rv901t.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/litex_acorn_baseboard.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import litex_acorn_baseboard
 

litex_boards/targets/logicbone.py

@@ -12,7 +12,7 @@ import sys
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import logicbone
 

litex_boards/targets/machdyne_krote.py

@@ -22,7 +22,7 @@ import sys
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import CRG
 

litex_boards/targets/machdyne_schoko.py

@@ -14,7 +14,7 @@ import json
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import machdyne_schoko
 

litex_boards/targets/micronova_mercury2.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import CRG
 

litex_boards/targets/mist.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/mnt_rkx7.py

@@ -9,7 +9,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import mnt_rkx7
 

litex_boards/targets/muselab_icesugar.py

@@ -11,7 +11,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import muselab_icesugar
 

litex_boards/targets/muselab_icesugar_pro.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/myminieye_runber.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *

litex_boards/targets/newae_cw305.py

@@ -13,7 +13,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import newae_cw305
 

litex_boards/targets/numato_aller.py

@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import numato_aller
 

litex_boards/targets/numato_mimas_a7.py

@@ -9,7 +9,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import numato_mimas_a7
 

litex_boards/targets/numato_nereid.py

@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import numato_nereid
 

litex_boards/targets/numato_tagus.py

@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import numato_tagus
 

litex_boards/targets/ocp_tap_timecard.py

@@ -27,7 +27,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import ocp_tap_timecard
 

litex_boards/targets/pano_logic_g2.py

@@ -11,7 +11,7 @@ import os
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import pano_logic_g2
 

litex_boards/targets/qmtech_10cl006.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/qmtech_5cefa2.py

@@ -10,7 +10,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/qmtech_ep4ce15_starter_kit.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/qmtech_ep4cex5.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/qmtech_ep4cgx150.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/qmtech_wukong.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import qmtech_wukong
 

litex_boards/targets/qmtech_xc7a35t.py

@@ -10,7 +10,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import qmtech_xc7a35t
 

litex_boards/targets/quicklogic_quickfeather.py

@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import quicklogic_quickfeather
 

litex_boards/targets/qwertyembedded_beaglewire.py

@@ -11,7 +11,7 @@ import os
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import qwertyembedded_beaglewire
 

litex_boards/targets/radiona_ulx3s.py

@@ -10,7 +10,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/radiona_ulx4m_ld_v2.py

@@ -17,7 +17,7 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 from litex_boards.platforms import radiona_ulx4m_ld_v2
 
 from litex.soc.cores.clock import *

litex_boards/targets/rcs_arctic_tern_bmc_card.py

@@ -11,7 +11,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import rcs_arctic_tern_bmc_card
 

litex_boards/targets/redpitaya.py

@@ -10,7 +10,7 @@ import os
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import redpitaya
 

litex_boards/targets/rz_easyfpga.py

@@ -10,7 +10,7 @@ from migen import *
 
 from litex.build.io import DDROutput
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import rz_easyfpga
 

litex_boards/targets/saanlima_pipistrello.py

@@ -15,7 +15,7 @@ from fractions import Fraction
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex_boards.platforms import saanlima_pipistrello
 

litex_boards/targets/scarabhardware_minispartan6.py

@@ -11,7 +11,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.io import DDROutput
 

litex_boards/targets/seeedstudio_spartan_edge_accelerator.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex.gen import LiteXModule
+from litex.gen import *
 
 from litex.build.generic_platform import *