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sds1104xe: Framebuffer fixes.

This commit is contained in:
Florent Kermarrec 2021-04-27 19:32:03 +02:00
parent 5bfeb999e4
commit f7ee3fa454
2 changed files with 6 additions and 5 deletions
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4
litex_boards/platforms/siglent_sds1104xe.py
View File

@ -39,9 +39,9 @@ _io = [ # Documented by https://github.com/360nosc0pe project.
Subsignal("clk", Pins("D20")), Subsignal("clk", Pins("D20")),
Subsignal("vsync", Pins("A21")), Subsignal("vsync", Pins("A21")),
Subsignal("hsync", Pins("A22")), Subsignal("hsync", Pins("A22")),
Subsignal("r", Pins("G22 F22 F21 F19 F18 F17")), Subsignal("r", Pins("D22 D21 C22 C20 B22 B21")),
Subsignal("g", Pins("F16 E21 E20 E19 E18 E16")), Subsignal("g", Pins("F16 E21 E20 E19 E18 E16")),
Subsignal("b", Pins("D22 D21 C22 C20 B22 B21")), Subsignal("b", Pins("G22 F22 F21 F19 F18 F17")),
IOStandard("LVCMOS33"), IOStandard("LVCMOS33"),
), ),

7
litex_boards/targets/siglent_sds1104xe.py
View File

@ -88,9 +88,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:4"), module = MT41K64M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192) l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_reverse = False,
) )
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------