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Merge pull request #593 from machdyne/master 

machdyne: fix typos; add vanille and lakritz
This commit is contained in:
Gwenhael Goavec-Merou 2024-06-22 21:43:02 +02:00 committed by GitHub
parent 95f5e030e5 cb43cdf6f9
commit f8d41e880d
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GPG Key ID: B5690EEEBB952194
22 changed files with 1940 additions and 267 deletions
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5
README.md
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@ -176,10 +176,15 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
├── machdyne_konfekt
├── machdyne_kopflos
├── machdyne_krote
├── machdyne_lakritz
├── machdyne_minze
├── machdyne_mozart_ml1
├── machdyne_mozart_ml2
├── machdyne_mozart_mx1
├── machdyne_noir
├── machdyne_schoko
├── machdyne_vanille
├── machdyne_vivaldi_ml1
├── marblemini
├── marble
├── micronova_mercury2

10
litex_boards/platforms/machdyne_konfekt.py
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@ -1,12 +1,12 @@
#
# This file is part of LiteX-Boards.
#
# Copright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
@ -129,7 +129,7 @@ _connectors_vx = [
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
@ -143,11 +143,11 @@ class Platform(LatticePlatform):
if revision == "v0": io += _io_v0
LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

10
litex_boards/platforms/machdyne_kopflos.py
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@ -1,12 +1,12 @@
#
# This file is part of LiteX-Boards.
#
# Copright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
# Copyright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
@ -135,7 +135,7 @@ _connectors_vx = [
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
@ -149,11 +149,11 @@ class Platform(LatticePlatform):
if revision == "v0": io += _io_v0
LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

144
litex_boards/platforms/machdyne_lakritz.py Normal file
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@ -0,0 +1,144 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io_vx = [
# Clock
("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("A2"), IOStandard("LVCMOS33")),
# SDRAM
("sdram_clock", 0, Pins("F16"), IOStandard("LVTTL33")),
("sdram", 0,
Subsignal("a", Pins(
"M13 M14 L14 L13 G12 G13 G14 G15",
"F12 F13 T15 F14 E14")),
Subsignal("ba", Pins("P14 N13")),
Subsignal("cs_n", Pins("G16")),
Subsignal("cke", Pins("F15")),
Subsignal("ras_n", Pins("J16")),
Subsignal("cas_n", Pins("K16")),
Subsignal("we_n", Pins("L15")),
Subsignal("dq", Pins(
"R15 R16 P15 P16 N16 N14 M16 M15",
"E16 D14 D16 C15 C16 C14 B16 B15")),
Subsignal("dm", Pins("L16 E15")),
IOStandard("LVTTL33")
),
# Differential Data Multiple Interface
("ddmi", 0,
Subsignal("clk_p", Pins("L1"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data0_p", Pins("M1"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data1_p", Pins("R2"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data2_p", Pins("R4"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
),
# USB-C
("usb", 0,
Subsignal("d_p", Pins("T6")),
Subsignal("d_n", Pins("R6")),
Subsignal("pullup", Pins("R7")),
IOStandard("LVCMOS33")
),
# USB HOST
("usb_host", 0,
#Subsignal("dp", Pins("A3")),
#Subsignal("dm", Pins("A4")),
Subsignal("dp", Pins("A3 B1")),
Subsignal("dm", Pins("A4 B2")),
IOStandard("LVCMOS33")
),
# 3.5MM AUDIO
("audio_pwm", 0,
Subsignal("left", Pins("M3")),
Subsignal("right", Pins("N1")),
IOStandard("LVCMOS33")
),
# 3.5MM VIDEO
("video_dac", 0,
Subsignal("data", Pins("P1 R1 P2 N3")),
IOStandard("LVCMOS33")
),
]
_io_v0 = [
# SD card w/ SD-mode interface
("sdcard", 0,
Subsignal("clk", Pins("F2"), Misc("PULLMODE=NONE")),
Subsignal("cmd", Pins("K1"), Misc("PULLMODE=NONE")),
Subsignal("data", Pins("F3 F1 K3 K2"), Misc("PULLMODE=NONE")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33")
),
# SD card w/ SPI interface
("spisdcard", 0,
Subsignal("clk", Pins("F2")),
Subsignal("mosi", Pins("K1")),
Subsignal("cs_n", Pins("K2")),
Subsignal("miso", Pins("F3")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
# UART PMOD
("serial", 0,
Subsignal("tx", Pins("PMODA:1")),
Subsignal("rx", Pins("PMODA:2")),
IOStandard("LVCMOS33")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors_vx = [
("PMODA", "B11 B12 B13 B14 A11 A12 A13 A14")
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, revision="v0", device="25F", toolchain="trellis", **kwargs):
assert revision in ["v0"]
assert device in ["12F", "25F", "45F", "85F"]
self.revision = revision
io = _io_vx
connectors = _connectors_vx
if revision == "v0": io += _io_v0
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

10
litex_boards/platforms/machdyne_minze.py
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@ -1,12 +1,12 @@
#
# This file is part of LiteX-Boards.
#
# Copright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
# Copyright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
@ -106,7 +106,7 @@ _connectors_vx = [
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
@ -120,11 +120,11 @@ class Platform(LatticePlatform):
if revision == "v0": io += _io_v0
LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

64
litex_boards/platforms/machdyne_mozart_ml1.py
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@ -1,12 +1,12 @@
#
# This file is part of LiteX-Boards.
#
# Copright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
# Copyright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
@ -15,6 +15,7 @@ _io_vx = [
# Clock
("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")),
("clk50", 0, Pins("C7"), IOStandard("LVCMOS33")),
# SDRAM
("sdram_clock", 0, Pins("F16"), IOStandard("LVTTL33")),
@ -63,10 +64,6 @@ _io_vx = [
),
# ETHERNET
("eth_clocks", 0,
Subsignal("ref_clk", Pins("C7")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rx_data", Pins("E4 D4"), Misc("PULLMODE=UP")),
Subsignal("tx_data", Pins("E6 D6")),
@ -76,23 +73,13 @@ _io_vx = [
IOStandard("LVCMOS33")
),
# DEBUG UART
("serial", 0,
Subsignal("tx", Pins("B3")),
Subsignal("rx", Pins("A2")),
IOStandard("LVCMOS33")
),
]
_io_v0 = [
# SD card w/ SD-mode interface
("sdcard", 0,
Subsignal("cd", Pins("A6"), Misc("PULLMODE=UP")),
Subsignal("clk", Pins("L3")),
Subsignal("cmd", Pins("M1"), Misc("DRIVE=8 PULLMODE=UP")),
Subsignal("data", Pins("L1 M2 M3 L2"), Misc("DRIVE=8 PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
Subsignal("cd", Pins("A6"), Misc("PULLMODE=NONE")),
Subsignal("clk", Pins("L3"), Misc("PULLMODE=NONE")),
Subsignal("cmd", Pins("M1"), Misc("PULLMODE=NONE")),
Subsignal("data", Pins("L1 M2 M3 L2"), Misc("PULLMODE=NONE")),
#Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33")
),
@ -105,23 +92,44 @@ _io_v0 = [
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
]
_io_v0 = [
# DEBUG UART
("serial", 0,
Subsignal("tx", Pins("B3")),
Subsignal("rx", Pins("A2")),
IOStandard("LVCMOS33")
),
]
_io_v2 = [
# DEBUG UART
("serial", 0,
Subsignal("tx", Pins("B4")),
Subsignal("rx", Pins("C4")),
IOStandard("LVCMOS33")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors_vx = [
("X", "A4 A3 B3 A2"),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, revision="v0", device="45F", toolchain="trellis", **kwargs):
assert revision in ["v0"]
def __init__(self, revision="v2", device="45F", toolchain="trellis", **kwargs):
assert revision in ["v0", "v1", "v2"]
assert device in ["12F", "25F", "45F", "85F"]
self.revision = revision
@ -129,12 +137,14 @@ class Platform(LatticePlatform):
connectors = _connectors_vx
if revision == "v0": io += _io_v0
if revision == "v1": io += _io_v0
if revision == "v2": io += _io_v2
LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

137
litex_boards/platforms/machdyne_mozart_ml2.py Normal file
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@ -0,0 +1,137 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io_vx = [
# Clock
("clk48", 0, Pins("C7"), IOStandard("LVCMOS33")),
# DDR3L
("ddram", 0,
Subsignal("a", Pins(
"R15 L13 P14 R14 L12 T14 N11 T13",
"P12 T15 C14 M13 E14 R13 M14 D14"),
IOStandard("SSTL135_I")),
Subsignal("ba", Pins("N16 K13 P16"), IOStandard("SSTL135_I")),
Subsignal("ras_n", Pins("L16"), IOStandard("SSTL135_I")),
Subsignal("cas_n", Pins("M16"), IOStandard("SSTL135_I")),
Subsignal("we_n", Pins("P15"), IOStandard("SSTL135_I")),
Subsignal("cs_n", Pins("M15"), IOStandard("SSTL135_I")),
Subsignal("dm", Pins("F13 J13"), IOStandard("SSTL135_I")),
Subsignal("dq", Pins(
"F14 E16 F12 F15 G13 B16 G12 B15",
"J14 J16 K15 K14 H14 K16 H13 J15"),
IOStandard("SSTL135_I"),
Misc("TERMINATION=75")),
Subsignal("dqs_p", Pins("D16 G16"), IOStandard("SSTL135D_I"),
Misc("TERMINATION=OFF DIFFRESISTOR=100")),
Subsignal("clk_p", Pins("C16"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("K12"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("L15"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("R12"), IOStandard("SSTL135_I")),
Misc("SLEWRATE=FAST")
),
# Differential Data Multiple Interface
("ddmi", 0,
Subsignal("clk_p", Pins("B10"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data0_p", Pins("A9"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data1_p", Pins("C8"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data2_p", Pins("A11"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
),
# USB-C
("usb", 0,
Subsignal("d_p", Pins("A13")),
Subsignal("d_n", Pins("A14")),
Subsignal("pullup", Pins("B14")),
IOStandard("LVCMOS33")
),
# DUAL USB HOST
("usb_host", 0,
Subsignal("dp", Pins("A5 A3")),
Subsignal("dm", Pins("A6 A4")),
IOStandard("LVCMOS33")
),
# ETHERNET
("eth_clocks", 0,
Subsignal("ref_clk", Pins("A7")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rx_data", Pins("B5 B4"), Misc("PULLMODE=UP")),
Subsignal("tx_data", Pins("C6 B6")),
Subsignal("tx_en", Pins("C5")),
Subsignal("crs_dv", Pins("E7"), Misc("PULLMODE=UP")),
Subsignal("rst_n", Pins("D7")),
IOStandard("LVCMOS33")
),
# DEBUG UART
("serial", 0,
Subsignal("tx", Pins("B3")),
Subsignal("rx", Pins("A2")),
IOStandard("LVCMOS33")
),
]
_io_v0 = [
# SD card w/ SPI interface
("spisdcard", 0,
Subsignal("clk", Pins("L1")),
Subsignal("mosi", Pins("L4")),
Subsignal("cs_n", Pins("L2")),
Subsignal("miso", Pins("L3")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors_vx = [
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, revision="v0", device="45F", toolchain="trellis", **kwargs):
assert revision in ["v0"]
assert device in ["12F", "25F", "45F", "85F"]
self.revision = revision
io = _io_vx
connectors = _connectors_vx
if revision == "v0": io += _io_v0
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

164
litex_boards/platforms/machdyne_mozart_mx1.py Normal file
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@ -0,0 +1,164 @@
#
# This file is part of LiteX-Boards.
#
#
# Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2024 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import Xilinx7SeriesPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io_vx = [
# Clock
("clk48", 0, Pins("F5"), IOStandard("LVCMOS33")),
("clk50", 0, Pins("D4"), IOStandard("LVCMOS33")),
# SDRAM
("sdram_clock", 0, Pins("C8"), IOStandard("LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"D15 D16 E15 E16 C9 D9 D8 C7",
"E6 D6 C16 D5 E5")),
Subsignal("ba", Pins("B9 A8")),
Subsignal("cs_n", Pins("A9")),
Subsignal("cke", Pins("C4")),
Subsignal("ras_n", Pins("B10")),
Subsignal("cas_n", Pins("A10")),
Subsignal("we_n", Pins("B11")),
Subsignal("dq", Pins(
"B16 A15 B15 A14 B14 A13 C13 A12",
"B6 C6 A5 B5 A4 B4 C3 A3")),
Subsignal("dm", Pins("B12 A7")),
IOStandard("LVTTL")
),
# Differential Data Multiple Interface
("ddmi", 0,
Subsignal("clk_p", Pins("C1"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("B1"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("E2"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("D1"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("F2"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("E1"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("G2"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("G1"), IOStandard("TMDS_33"))
),
# USB-C
("usb", 0,
Subsignal("d_p", Pins("B2")),
Subsignal("d_n", Pins("A2")),
Subsignal("pullup", Pins("C2")),
IOStandard("LVCMOS33")
),
# DUAL USB HOST
("usb_host", 0,
Subsignal("dp", Pins("H2 K1")),
Subsignal("dm", Pins("H1 J1")),
IOStandard("LVCMOS33")
),
# ETHERNET
("eth", 0,
Subsignal("rx_data", Pins("F3 F4"), Misc("PULLUP")),
Subsignal("tx_data", Pins("D3 E3")),
Subsignal("tx_en", Pins("G4")),
Subsignal("crs_dv", Pins("H3"), Misc("PULLUP")),
Subsignal("rst_n", Pins("H4")),
IOStandard("LVCMOS33")
),
# LVDS
("lvds", 0,
Subsignal("tx_p", Pins("R2")),
Subsignal("tx_n", Pins("R1")),
Subsignal("rx_p", Pins("T4")),
Subsignal("rx_n", Pins("T3")),
IOStandard("LVDS_25")
),
# MMOD
("spiflash4x", 0,
Subsignal("cs_n", Pins("L12")),
#Subsignal("clk", Pins("")), # Accessed through STARTUPE2
Subsignal("dq", Pins("J13 J14 K15 K16")),
IOStandard("LVCMOS33")
),
# DEBUG UART
("serial", 0,
Subsignal("tx", Pins("L2")),
Subsignal("rx", Pins("L3")),
IOStandard("LVCMOS33")
),
]
_io_v0 = [
# SD card w/ SD-mode interface
("sdcard", 0,
Subsignal("cd", Pins("K3")),
Subsignal("clk", Pins("R6")),
Subsignal("cmd", Pins("T8")),
Subsignal("data", Pins("T7 P8 T9 T5")),
IOStandard("LVCMOS33")
),
# SD card w/ SPI interface
("spisdcard", 0,
Subsignal("clk", Pins("R6")),
Subsignal("mosi", Pins("T8")),
Subsignal("cs_n", Pins("T5")),
Subsignal("miso", Pins("T7")),
IOStandard("LVCMOS33"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors_vx = [
]
# Platform -----------------------------------------------------------------------------------------
class Platform(Xilinx7SeriesPlatform):
def __init__(self, revision="v0", variant="a7-35", toolchain="vivado"):
assert revision in ["v0"]
self.revision = revision
io = _io_vx
connectors = _connectors_vx
if revision == "v0": io += _io_v0
device = {
"a7-35": "xc7a35tftg256-1"
}[variant]
Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
def do_finalize(self, fragment):
Xilinx7SeriesPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)

14
litex_boards/platforms/machdyne_noir.py
View File

@ -1,12 +1,12 @@
#
# This file is part of LiteX-Boards.
#
# Copright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
@ -110,8 +110,8 @@ _io_v0 = [
("sdcard", 0,
Subsignal("cd", Pins("A5")),
Subsignal("clk", Pins("B4")),
Subsignal("cmd", Pins("A3")),
Subsignal("data", Pins("A4 B5 A2 B3")),
Subsignal("cmd", Pins("A3"), Misc("PULLMODE=UP")),
Subsignal("data", Pins("A4 B5 A2 B3"), Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33")
),
@ -135,7 +135,7 @@ _connectors_vx = [
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
@ -149,11 +149,11 @@ class Platform(LatticePlatform):
if revision == "v0": io += _io_v0
LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

25
litex_boards/platforms/machdyne_schoko.py
View File

@ -1,7 +1,7 @@
#
# This file is part of LiteX-Boards.
#
# Copright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
@ -77,8 +77,10 @@ _io_vx = [
# USB HOST
("usb_host", 0,
Subsignal("dp", Pins("F2")),
Subsignal("dm", Pins("E1")),
Subsignal("dp", Pins("PMODB:0 PMODB:2")),
Subsignal("dm", Pins("PMODB:1 PMODB:3")),
#Subsignal("dp", Pins("F2 PMODB:0")),
#Subsignal("dm", Pins("E1 PMODB:1")),
IOStandard("LVCMOS33")
),
@ -103,20 +105,6 @@ _io_vx = [
_io_v1 = [
# SD card w/ SPI interface
("spisdcard", 0,
Subsignal("clk", Pins("D6")),
Subsignal("mosi", Pins("C6")),
Subsignal("cs_n", Pins("B6")),
Subsignal("miso", Pins("E6")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
]
_io_v2 = [
# SD card w/ SD-mode interface
("sdcard", 0,
Subsignal("cd", Pins("A13")),
@ -143,14 +131,13 @@ class Platform(LatticeECP5Platform):
def __init__(self, revision="v1", device="45F", toolchain="trellis", **kwargs):
assert revision in ["v1", "v2"]
assert device in ["25F", "45F", "85F"]
assert device in ["12F", "25F", "45F", "85F"]
self.revision = revision
io = _io_vx
connectors = _connectors_vx
if revision == "v1": io += _io_v1
if revision == "v2": io += _io_v2
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)

119
litex_boards/platforms/machdyne_vanille.py Normal file
View File

@ -0,0 +1,119 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io_vx = [
# Clock
("clk48", 0, Pins("128"), IOStandard("LVCMOS33")),
# LED
("user_led", 0, Pins("52"), IOStandard("LVCMOS33")),
# SDRAM
("sdram_clock", 0, Pins("72"), IOStandard("LVTTL33")),
("sdram", 0,
Subsignal("a", Pins(
"81 80 79 78 105 106 107 108 "
"110 111 82 112 113")),
Subsignal("ba", Pins("92 91")),
Subsignal("cs_n", Pins("84")),
Subsignal("cke", Pins("114")),
Subsignal("ras_n", Pins("88")),
Subsignal("cas_n", Pins("89")),
Subsignal("we_n", Pins("90")),
Subsignal("dq", Pins(
"104 103 102 99 98 97 95 94 ",
"116 117 118 119 120 121 124 125")),
Subsignal("dm", Pins("93 115")),
IOStandard("LVTTL33")
),
# Differential Data Multiple Interface
("ddmi", 0,
Subsignal("clk_p", Pins("69"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data0_p", Pins("71"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data1_p", Pins("74"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data2_p", Pins("77"),
IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
),
# USB-C
("usb", 0,
Subsignal("d_p", Pins("40")),
Subsignal("d_n", Pins("44")),
Subsignal("pullup", Pins("45")),
IOStandard("LVCMOS33")
),
# USB HOST
("usb_host", 0,
Subsignal("dp", Pins("39")),
Subsignal("dm", Pins("41")),
IOStandard("LVCMOS33")
),
# DEBUG UART (on USB host port)
#("serial", 0,
# Subsignal("tx", Pins("39")),
# Subsignal("rx", Pins("41")),
# IOStandard("LVCMOS33")
#),
]
_io_v0 = [
# SD card w/ SPI interface
("spisdcard", 0,
Subsignal("clk", Pins("50")),
Subsignal("mosi", Pins("47")),
Subsignal("cs_n", Pins("48")),
Subsignal("miso", Pins("46")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors_vx = [
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, revision="v0", device="12F", toolchain="trellis", **kwargs):
assert revision in ["v0"]
assert device in ["12F", "25F", "45F", "85F"]
self.revision = revision
io = _io_vx
connectors = _connectors_vx
if revision == "v0": io += _io_v0
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6TG144", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

144
litex_boards/platforms/machdyne_vivaldi_ml1.py Normal file
View File

@ -0,0 +1,144 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticeECP5Platform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io_vx = [
# Clock
("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")),
("clk50", 0, Pins("C7"), IOStandard("LVCMOS33")),
# SDRAM
("sdram_clock", 0, Pins("F16"), IOStandard("LVTTL33")),
("sdram", 0,
Subsignal("a", Pins(
"M13 M14 L14 L13 G12 G13 G14 G15",
"F12 F13 T15 F14 E14")),
Subsignal("ba", Pins("P14 N13")),
Subsignal("cs_n", Pins("J16")),
Subsignal("cke", Pins("F15")),
Subsignal("ras_n", Pins("K15")),
Subsignal("cas_n", Pins("K16")),
Subsignal("we_n", Pins("L15")),
Subsignal("dq", Pins(
"R15 R16 P16 P15 N16 N14 M16 M15",
"E15 D16 D14 C16 C15 C14 B15 B16")),
Subsignal("dm", Pins("L16 E16")),
IOStandard("LVTTL33")
),
# I2C
("i2c", 0,
Subsignal("sda", Pins("A13")),
Subsignal("scl", Pins("A11")),
IOStandard("LVCMOS33")
),
# DUAL USB HOST
("usb_host", 0,
Subsignal("dp", Pins("A9 C8")),
Subsignal("dm", Pins("A10 B8")),
IOStandard("LVCMOS33")
),
# ETHERNET
("eth", 0,
Subsignal("rx_data", Pins("E4 D4"), Misc("PULLMODE=UP")),
Subsignal("tx_data", Pins("E6 D6")),
Subsignal("tx_en", Pins("C5")),
Subsignal("crs_dv", Pins("A5"), Misc("PULLMODE=UP")),
Subsignal("rst_n", Pins("B5")),
IOStandard("LVCMOS33")
),
("eth", 1,
Subsignal("rx_data", Pins("B3 A2"), Misc("PULLMODE=UP")),
Subsignal("tx_data", Pins("A4 A3")),
Subsignal("tx_en", Pins("R12")),
Subsignal("crs_dv", Pins("T13"), Misc("PULLMODE=UP")),
Subsignal("rst_n", Pins("T14")),
IOStandard("LVCMOS33")
),
# SD card w/ SD-mode interface
("sdcard", 0,
Subsignal("cd", Pins("A6")),
Subsignal("clk", Pins("L3")),
Subsignal("cmd", Pins("M1")),
Subsignal("data", Pins("L1 M2 M3 L2")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33")
),
# SD card w/ SPI interface
("spisdcard", 0,
Subsignal("clk", Pins("L3")),
Subsignal("mosi", Pins("M1")),
Subsignal("cs_n", Pins("L2")),
Subsignal("miso", Pins("L1")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
]
_io_v0 = [
# DEBUG UART
("serial", 0,
Subsignal("tx", Pins("B3")),
Subsignal("rx", Pins("A2")),
IOStandard("LVCMOS33")
),
]
_io_v2 = [
# DEBUG UART
("serial", 0,
Subsignal("tx", Pins("B4")),
Subsignal("rx", Pins("C4")),
IOStandard("LVCMOS33")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors_vx = [
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticeECP5Platform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, revision="v2", device="45F", toolchain="trellis", **kwargs):
assert revision in ["v0", "v1", "v2"]
assert device in ["12F", "25F", "45F", "85F"]
self.revision = revision
io = _io_vx
connectors = _connectors_vx
if revision == "v0": io += _io_v0
if revision == "v1": io += _io_v0
if revision == "v2": io += _io_v2
LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, cable):
return OpenFPGALoader(cable=cable)
def do_finalize(self, fragment):
LatticeECP5Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

62
litex_boards/targets/machdyne_konfekt.py
View File

@ -18,7 +18,6 @@ from litex.gen import *
from litex_boards.platforms import machdyne_konfekt
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.build.io import DDROutput
from litex.soc.cores.clock import *
@ -40,7 +39,7 @@ from litex.soc.integration.soc import SoCRegion
# CRG ---------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, sdram_rate):
def __init__(self, platform, sys_clk_freq, sdram_rate = "1:2"):
self.rst = Signal()
self.cd_por = ClockDomain()
self.cd_sys = ClockDomain()
@ -109,7 +108,7 @@ class BaseSoC(SoCCore):
}}
def __init__(self, revision="v0", device="12F", sdram_device="W9825G6KH6", sdram_rate="1:2", sys_clk_freq=int(40e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, **kwargs):
platform = machdyne_konfekt.Platform(revision=revision, device=device ,toolchain=toolchain)
platform = machdyne_konfekt.Platform(revision=revision, device=device, toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
@ -165,45 +164,26 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Konfekt")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=40e6, help="System clock frequency.")
target_group.add_argument("--revision", default="v0", help="Board Revision (v0).")
target_group.add_argument("--device", default="12F", help="ECP5 device (25F, 45F or 85F).")
target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
target_group.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
target_group.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
target_group.add_argument("--sdram-device", default="W9825G6KH6", help="SDRAM device (W9825G6KH6 or IS42S16320).")
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_konfekt.Platform, description="LiteX SoC on Konfekt")
parser.add_argument("--sys-clk-freq", default=40e6, help="System clock frequency.")
parser.add_argument("--revision", default="v0", help="Board Revision (v0).")
parser.add_argument("--device", default="12F", help="ECP5 device (12F, 25F, 45F or 85F).")
parser.add_argument("--cable", default="dirtyJtag", help="OpenFPGALoader cable type.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--sdram-device", default="W9825G6KH6", help="SDRAM device (W9825G6KH6 or IS42S16320).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
print("")
print("")
print("")
print(args)
print("")
print("")
print("")
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sys_clk_freq = int(float(args.sys_clk_freq)),
revision = args.revision,
device = args.device,
sdram_device = args.sdram_device,
with_usb_host = args.with_usb_host,
**soc_core_argdict(args))
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
@ -211,19 +191,13 @@ def main():
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**builder_kargs)
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer(args.cable)
prog = soc.platform.create_programmer(cable=args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer(args.cable)
prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()

47
litex_boards/targets/machdyne_kopflos.py
View File

@ -106,7 +106,7 @@ class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v0", device="12F", sdram_device="MT41K128M16", sdram_rate="1:2", sys_clk_freq=int(50e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, with_ethernet=False, **kwargs):
def __init__(self, revision="v0", device="12F", sdram_device="MT41K128M16", sdram_rate="1:2", sys_clk_freq=int(40e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, with_ethernet=False, **kwargs):
platform = machdyne_kopflos.Platform(revision=revision, device=device ,toolchain=toolchain)
@ -166,27 +166,18 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Schoko")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--revision", default="v0", help="Board Revision (v0).")
target_group.add_argument("--device", default="12F", help="ECP5 device (12F, 25F, 45F or 85F).")
target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
target_group.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
target_group.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
target_group.add_argument("--sdram-device", default="MT41K128M16", help="SDRAM device.")
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_kopflos.Platform, description="LiteX SoC on Schoko")
parser.add_argument("--sys-clk-freq", default=40e6, help="System clock frequency.")
parser.add_argument("--revision", default="v0", help="Board Revision (v0).")
parser.add_argument("--device", default="12F", help="ECP5 device (12F, 25F, 45F or 85F).")
parser.add_argument("--cable", default="dirtyJtag", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
parser.add_argument("--sdram-device", default="MT41K128M16", help="SDRAM device.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
@ -197,7 +188,7 @@ def main():
sdram_device = args.sdram_device,
with_usb_host = args.with_usb_host,
with_ethernet = args.with_ethernet,
**soc_core_argdict(args))
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
@ -205,19 +196,13 @@ def main():
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**builder_kargs)
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer(args.cable)
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer(args.cable)
prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()

207
litex_boards/targets/machdyne_lakritz.py Executable file
View File

@ -0,0 +1,207 @@
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
#
import os
import sys
import json
from migen import *
from litex.gen import *
from litex_boards.platforms import machdyne_lakritz
from litex.build.io import DDROutput
from litex.soc.cores.clock import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.usb_ohci import USBOHCI
from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.video import VideoHDMIPHY
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litedram.modules import W9825G6KH6
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litex.soc.integration.soc import SoCRegion
# CRG ---------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, sdram_rate = "1:2"):
self.rst = Signal()
self.cd_por = ClockDomain()
self.cd_sys = ClockDomain()
self.cd_video = ClockDomain()
self.cd_video5x = ClockDomain()
# Clk / Rst
clk48 = platform.request("clk48")
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | self.rst)
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
self.cd_sys2x = ClockDomain()
self.cd_sys2x_ps = ClockDomain()
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
elif sdram_rate == "1:4":
self.cd_sys2x = ClockDomain()
self.cd_sys4x = ClockDomain()
self.cd_sys4x_ps = ClockDomain()
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_ps, 4*sys_clk_freq, phase=180)
else:
self.cd_sys_ps = ClockDomain()
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
if sdram_rate == "1:2":
sdram_clk = ClockSignal("sys2x_ps")
elif sdram_rate == "1:4":
sdram_clk = ClockSignal("sys4x_ps")
else:
sdram_clk = ClockSignal("sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
pll2 = ECP5PLL()
self.pll2 = pll2
pll2.register_clkin(clk48, 48e6)
pll2.create_clkout(self.cd_video, 25e6)
pll2.create_clkout(self.cd_video5x, 125e6)
self.cd_usb_12 = ClockDomain()
self.cd_usb = ClockDomain()
self.cd_usb_48 = ClockDomain()
self.cd_usb_48 = self.cd_usb
pll2.create_clkout(self.cd_usb, 48e6)
pll2.create_clkout(self.cd_usb_12, 12e6)
self.comb += pll2.reset.eq(~por_done)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v0", device="25F", sdram_device="W9825G6KH6", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=False, with_video_framebuffer=False, with_usb_host=False, **kwargs):
platform = machdyne_lakritz.Platform(revision=revision, device=device ,toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Lakritz", **kwargs)
# DRAM -------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
if sdram_rate == "1:2":
sdrphy_cls = HalfRateGENSDRPHY
elif sdram_rate == "1:4":
from litedram.phy import QuarterRateGENSDRPHY
sdrphy_cls = QuarterRateGENSDRPHY
else:
sdrphy_cls = GENSDRPHY
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
if sdram_device == "W9825G6KH6":
self.add_sdram("sdram",
phy = self.sdrphy,
module = W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 0)
)
if sdram_device == "IS42S16320":
self.add_sdram("sdram",
phy = self.sdrphy,
module = IS42S16320(self.clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 0)
)
# USB Host ---------------------------------------------------------------------------------
if with_usb_host:
self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
# DDMI Framebuffer -------------------------------------------------------------------------------------
if with_video_framebuffer:
self.videophy = VideoHDMIPHY(platform.request("ddmi"),
clock_domain="video")
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@60Hz",
clock_domain="video",
format="rgb565")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_lakritz.Platform, description="LiteX SoC on Lakritz")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--revision", default="v0", help="Board Revision (v0).")
parser.add_argument("--device", default="25F", help="ECP5 device (12F, 25F, 45F or 85F).")
parser.add_argument("--cable", default="dirtyJtag", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-video-framebuffer", action="store_true", help="Enable DDMI framebuffer.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--sdram-device", default="W9825G6KH6", help="SDRAM device (W9825G6KH6 or IS42S16320).")
args = parser.parse_args()
soc = BaseSoC(
revision = args.revision,
device = args.device,
sys_clk_freq = int(float(args.sys_clk_freq)),
sdram_device = args.sdram_device,
with_usb_host = args.with_usb_host,
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()

63
litex_boards/targets/machdyne_minze.py
View File

@ -18,7 +18,6 @@ from litex.gen import *
from litex_boards.platforms import machdyne_minze
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.build.io import DDROutput
from litex.soc.cores.clock import *
@ -95,7 +94,7 @@ class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v0", device="12F", sdram_device="W9825G6KH6", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, **kwargs):
def __init__(self, revision="v0", device="12F", sdram_device="W9825G6KH6", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=False, with_usb_host=False, **kwargs):
platform = machdyne_minze.Platform(revision=revision, device=device ,toolchain=toolchain)
@ -148,45 +147,28 @@ class BaseSoC(SoCCore):
# clock_domain="video")
# Leds -------------------------------------------------------------------------------------
#if with_led_chaser:
# self.leds = LedChaser(
# pads = platform.request_all("user_led"),
# sys_clk_freq = sys_clk_freq)
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Minze")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
target_group.add_argument("--revision", default="v0", help="Board Revision (v0).")
target_group.add_argument("--device", default="12F", help="ECP5 device (25F, 45F or 85F).")
target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
target_group.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
target_group.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
target_group.add_argument("--sdram-device", default="W9825G6KH6", help="SDRAM device (W9825G6KH6 or IS42S16320).")
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_minze.Platform, description="LiteX SoC on Minze")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--revision", default="v0", help="Board Revision (v0).")
parser.add_argument("--device", default="12F", help="ECP5 device (25F, 45F or 85F).")
parser.add_argument("--cable", default="dirtyJtag", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
parser.add_argument("--sdram-device", default="W9825G6KH6", help="SDRAM device (W9825G6KH6 or IS42S16320).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
print("")
print("")
print("")
print(args)
print("")
print("")
print("")
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
@ -194,7 +176,7 @@ def main():
sys_clk_freq = int(float(args.sys_clk_freq)),
sdram_device = args.sdram_device,
with_usb_host = args.with_usb_host,
**soc_core_argdict(args))
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
@ -202,19 +184,14 @@ def main():
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**builder_kargs)
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer(args.cable)
prog = soc.platform.create_programmer(cable=args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer(args.cable)
prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()

62
litex_boards/targets/machdyne_mozart_ml1.py
View File

@ -20,8 +20,6 @@ from litex_boards.platforms import machdyne_mozart_ml1
from litex.build.io import DDROutput
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock import *
@ -47,12 +45,14 @@ class _CRG(LiteXModule):
self.cd_init = ClockDomain()
self.cd_video = ClockDomain()
self.cd_video5x = ClockDomain()
self.cd_eth = ClockDomain()
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk48 = platform.request("clk48")
clk50 = platform.request("clk50")
# Power on reset
por_count = Signal(16, reset=2**16-1)
@ -94,9 +94,11 @@ class _CRG(LiteXModule):
pll2 = ECP5PLL()
self.pll2 = pll2
pll2.register_clkin(clk48, 48e6)
pll2.register_clkin(clk50, 50e6)
pll2.create_clkout(self.cd_eth, 50e6)
pll2.create_clkout(self.cd_video, 25e6)
pll2.create_clkout(self.cd_video5x, 125e6)
self.comb += pll2.reset.eq(~por_done)
pll3 = ECP5PLL()
self.pll3 = pll3
@ -115,7 +117,7 @@ class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v0", device="45F", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_usb_host=False, with_ethernet=False, **kwargs):
def __init__(self, revision="v2", device="45F", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_usb_host=False, with_ethernet=False, **kwargs):
platform = machdyne_mozart_ml1.Platform(revision=revision, device=device ,toolchain=toolchain)
@ -158,35 +160,29 @@ class BaseSoC(SoCCore):
if with_ethernet:
from liteeth.phy.rmii import LiteEthPHYRMII
self.ethphy = LiteEthPHYRMII(
clock_pads = platform.request("eth_clocks"),
#clock_pads = platform.request("eth_clocks"),
clock_pads=None,
pads = platform.request("eth"),
with_hw_init_reset=True,
refclk_cd=None)
refclk_cd="eth")
#refclk_cd=None)
self.add_ethernet(phy=self.ethphy)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Mozart ML1")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
target_group.add_argument("--revision", default="v0", help="Board Revision (v0).")
target_group.add_argument("--device", default="45F", help="ECP5 device (12F, 25F, 45F or 85F).")
target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
target_group.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
target_group.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_mozart_ml1.Platform, description="LiteX SoC on Mozart ML1")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--revision", default="v2", help="Board Revision (v0, v1, v2).")
parser.add_argument("--device", default="45F", help="ECP5 device (12F, 25F, 45F or 85F).")
parser.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
parser.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
@ -196,27 +192,21 @@ def main():
sys_clk_freq = int(float(args.sys_clk_freq)),
with_usb_host = args.with_usb_host,
with_ethernet = args.with_ethernet,
**soc_core_argdict(args))
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
soc.add_sdcard(software_debug=False)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**builder_kargs)
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer(args.cable)
prog = soc.platform.create_programmer(cable=args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer(args.cable)
prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()

220
litex_boards/targets/machdyne_mozart_ml2.py Executable file
View File

@ -0,0 +1,220 @@
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) Greg Davill <greg.davill@gmail.com>
# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
#
import os
import sys
import json
from migen import *
from litex.gen import *
from litex_boards.platforms import machdyne_mozart_ml2
from litex.build.io import DDROutput
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock import *
from litex.soc.cores.usb_ohci import USBOHCI
from litex.soc.cores.video import VideoHDMIPHY
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.interconnect.csr_eventmanager import *
from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
from litedram.phy import ECP5DDRPHY
from litex.soc.integration.soc import SoCRegion
# CRG ---------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, sdram_rate):
self.rst = Signal()
self.cd_por = ClockDomain()
self.cd_sys = ClockDomain()
self.cd_sys2x = ClockDomain()
self.cd_sys2x_i = ClockDomain()
self.cd_init = ClockDomain()
self.cd_video = ClockDomain()
self.cd_video5x = ClockDomain()
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk48 = platform.request("clk48")
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
sys2x_clk_ecsout = Signal()
self.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | self.rst)
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 24e6)
self.specials += [
Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk,
i_SEL = 0,
o_ECSOUT = sys2x_clk_ecsout),
Instance("ECLKSYNCB",
i_ECLKI = sys2x_clk_ecsout,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
pll2 = ECP5PLL()
self.pll2 = pll2
pll2.register_clkin(clk48, 48e6)
pll2.create_clkout(self.cd_video, 25e6)
pll2.create_clkout(self.cd_video5x, 125e6)
pll3 = ECP5PLL()
self.pll3 = pll3
pll3.register_clkin(clk48, 48e6)
self.cd_usb_12 = ClockDomain()
self.cd_usb = ClockDomain()
self.cd_usb_48 = ClockDomain()
self.cd_usb_48 = self.cd_usb
pll3.create_clkout(self.cd_usb, 48e6)
pll3.create_clkout(self.cd_usb_12, 12e6)
self.comb += pll3.reset.eq(~por_done)
#pll4 = ECP5PLL()
#self.pll4 = pll4
#pll4.register_clkin(clk48, 48e6)
#pll4.create_clkout(self.cd_eth, 50e6)
#self.comb += pll4.reset.eq(~por_done)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v0", device="45F", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_usb_host=False, with_ethernet=False, sdram_device="MT41K256M16", **kwargs):
platform = machdyne_mozart_ml2.Platform(revision=revision, device=device ,toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Mozart ML2", **kwargs)
# DDR3L -------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K64M16": MT41K64M16,
"MT41K128M16": MT41K128M16,
"MT41K256M16": MT41K256M16,
"MT41K512M16": MT41K512M16,
}
sdram_module = available_sdram_modules.get(sdram_device)
ddram_pads = platform.request("ddram")
self.ddrphy = ECP5DDRPHY(
pads = ddram_pads,
sys_clk_freq = sys_clk_freq,
cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
self.ddrphy.settings.rtt_nom = "disabled"
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = sdram_module(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# DDMI Framebuffer -------------------------------------------------------------------------------------
self.videophy = VideoHDMIPHY(platform.request("ddmi"),
clock_domain="video")
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz",
clock_domain="video", format="rgb565")
# USB Host ---------------------------------------------------------------------------------
if with_usb_host:
self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
from liteeth.phy.rmii import LiteEthPHYRMII
self.ethphy = LiteEthPHYRMII(
clock_pads = platform.request("eth_clocks"),
pads = platform.request("eth"),
with_hw_init_reset=True,
refclk_cd=None)
self.add_ethernet(phy=self.ethphy)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_mozart_ml2.Platform, description="LiteX SoC on Mozart ML2")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--revision", default="v0", help="Board Revision (v0).")
parser.add_argument("--device", default="45F", help="ECP5 device (12F, 25F, 45F or 85F).")
parser.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
parser.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
parser.add_argument("--sdram-device", default="MT41K256M16", help="SDRAM device.")
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_usb_host = args.with_usb_host,
with_ethernet = args.with_ethernet,
sdram_device = args.sdram_device,
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer(cable=args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()

220
litex_boards/targets/machdyne_mozart_mx1.py Executable file
View File

@ -0,0 +1,220 @@
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
#
import os
import sys
import json
from migen import *
from litex.gen import *
from litex_boards.platforms import machdyne_mozart_mx1
from litex.build.io import DDROutput
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock import *
from litex.soc.cores.usb_ohci import USBOHCI
from litex.soc.cores.video import VideoS7HDMIPHY
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.interconnect.csr_eventmanager import *
from litedram.modules import W9825G6KH6
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litex.soc.integration.soc import SoCRegion
# CRG ---------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, sdram_rate):
self.rst = Signal()
self.cd_por = ClockDomain()
self.cd_sys = ClockDomain()
self.cd_init = ClockDomain()
self.cd_eth = ClockDomain()
self.cd_video = ClockDomain()
self.cd_video5x = ClockDomain()
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk48 = platform.request("clk48")
clk50 = platform.request("clk50")
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.pll = pll = S7PLL()
self.comb += pll.reset.eq(~por_done | self.rst)
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
self.cd_sys2x = ClockDomain()
self.cd_sys2x_ps = ClockDomain()
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
elif sdram_rate == "1:4":
self.cd_sys2x = ClockDomain()
self.cd_sys4x = ClockDomain()
self.cd_sys4x_ps = ClockDomain()
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_ps, 4*sys_clk_freq, phase=180)
else:
self.cd_sys_ps = ClockDomain()
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
if sdram_rate == "1:2":
sdram_clk = ClockSignal("sys2x_ps")
elif sdram_rate == "1:4":
sdram_clk = ClockSignal("sys4x_ps")
else:
sdram_clk = ClockSignal("sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
pll2 = S7PLL()
self.pll2 = pll2
pll2.register_clkin(clk50, 50e6)
pll2.create_clkout(self.cd_eth, 50e6)
pll2.create_clkout(self.cd_video, 25e6)
pll2.create_clkout(self.cd_video5x, 125e6)
pll3 = S7PLL()
self.pll3 = pll3
pll3.register_clkin(clk48, 48e6)
self.cd_usb_12 = ClockDomain()
self.cd_usb = ClockDomain()
self.cd_usb_48 = ClockDomain()
self.cd_usb_48 = self.cd_usb
pll3.create_clkout(self.cd_usb, 48e6)
pll3.create_clkout(self.cd_usb_12, 12e6)
self.comb += pll3.reset.eq(~por_done)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v0", variant="a7-35", toolchain="vivado", sdram_rate="1:2", sys_clk_freq=int(80e6), with_usb_host=False, with_ethernet=False, with_xadc=False, **kwargs):
#def __init__(self, revision="v0", variant="a7-35", toolchain="yosys+nextpnr", sdram_rate="1:2", sys_clk_freq=int(48e6), with_usb_host=False, with_ethernet=False, **kwargs):
platform = machdyne_mozart_mx1.Platform(revision=revision, variant=variant, toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Mozart ML1", **kwargs)
# DRAM -------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
if sdram_rate == "1:2":
sdrphy_cls = HalfRateGENSDRPHY
elif sdram_rate == "1:4":
sdrphy_cls = QuarterRateGENSDRPHY
else:
sdrphy_cls = GENSDRPHY
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# XADC -------------------------------------------------------------------------------------
if with_xadc:
self.xadc = XADC()
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q32
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
# DDMI Framebuffer -------------------------------------------------------------------------------------
self.videophy = VideoS7HDMIPHY(platform.request("ddmi"),
clock_domain="video")
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz",
clock_domain="video", format="rgb565")
# USB Host ---------------------------------------------------------------------------------
if with_usb_host:
self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
from liteeth.phy.rmii import LiteEthPHYRMII
self.ethphy = LiteEthPHYRMII(
#clock_pads = platform.request("eth_clocks"),
clock_pads=None,
pads = platform.request("eth"),
with_hw_init_reset=True,
refclk_cd="eth")
#refclk_cd=None)
self.add_ethernet(phy=self.ethphy)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_mozart_mx1.Platform, description="LiteX SoC on Mozart MX1.")
parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
parser.add_argument("--revision", default="v0", help="Board Revision (v0).")
parser.add_argument("--device", default="45F", help="ECP5 device (12F, 25F, 45F or 85F).")
parser.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
parser.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_usb_host = args.with_usb_host,
with_ethernet = args.with_ethernet,
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
if __name__ == "__main__":
main()

66
litex_boards/targets/machdyne_noir.py
View File

@ -19,7 +19,6 @@ from litex.gen import *
from litex_boards.platforms import machdyne_noir
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.build.io import DDROutput
from migen.genlib.resetsync import AsyncResetSynchronizer
@ -41,7 +40,7 @@ from litex.soc.integration.soc import SoCRegion
# CRG ---------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, sdram_rate):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.cd_por = ClockDomain()
self.cd_sys = ClockDomain()
@ -109,15 +108,15 @@ class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v0", device="45F", sdram_device="MT41K128M16", sdram_rate="1:2", sys_clk_freq=int(40e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, with_ethernet=False, **kwargs):
def __init__(self, revision="v0", device="45F", sdram_device="MT41K128M16", sys_clk_freq=int(50e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, with_ethernet=False, **kwargs):
platform = machdyne_noir.Platform(revision=revision, device=device ,toolchain=toolchain)
platform = machdyne_noir.Platform(revision=revision, device=device, toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Schoko", **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Noir", **kwargs)
# DDR3L ----------------------------------------------------------------------------------
@ -166,47 +165,29 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Schoko")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=40e6, help="System clock frequency.")
target_group.add_argument("--revision", default="v0", help="Board Revision (v0).")
target_group.add_argument("--device", default="45F", help="ECP5 device (25F, 45F or 85F).")
target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
target_group.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
target_group.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
target_group.add_argument("--sdram-device", default="MT41K128M16", help="SDRAM device.")
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_noir.Platform, description="LiteX SoC on Noir")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--revision", default="v0", help="Board Revision (v0).")
parser.add_argument("--device", default="45F", help="ECP5 device (25F, 45F or 85F).")
parser.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
parser.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
parser.add_argument("--sdram-device", default="MT41K128M16", help="SDRAM device.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
print("")
print("")
print("")
print(args)
print("")
print("")
print("")
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sys_clk_freq = int(float(args.sys_clk_freq)),
sdram_device = args.sdram_device,
with_usb_host = args.with_usb_host,
with_ethernet = args.with_ethernet,
**soc_core_argdict(args))
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
@ -214,19 +195,14 @@ def main():
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**builder_kargs)
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer(args.cable)
prog = soc.platform.create_programmer(cable=args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer(args.cable)
prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()

200
litex_boards/targets/machdyne_vanille.py Executable file
View File

@ -0,0 +1,200 @@
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
#
import os
import sys
import json
from migen import *
from litex.gen import *
from litex_boards.platforms import machdyne_vanille
from litex.build.io import DDROutput
from litex.soc.cores.clock import *
from litex.soc.cores.usb_ohci import USBOHCI
from litex.soc.cores.video import VideoHDMIPHY
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litedram.modules import W9825G6KH6
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litex.soc.integration.soc import SoCRegion
# CRG ---------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, sdram_rate):
self.cd_por = ClockDomain()
self.cd_sys = ClockDomain()
self.cd_video = ClockDomain()
self.cd_video5x = ClockDomain()
# Clk / Rst
clk48 = platform.request("clk48")
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done)
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
self.cd_sys2x = ClockDomain()
self.cd_sys2x_ps = ClockDomain()
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
elif sdram_rate == "1:4":
self.cd_sys2x = ClockDomain()
self.cd_sys4x = ClockDomain()
self.cd_sys4x_ps = ClockDomain()
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_ps, 4*sys_clk_freq, phase=180)
else:
self.cd_sys_ps = ClockDomain()
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
if sdram_rate == "1:2":
sdram_clk = ClockSignal("sys2x_ps")
elif sdram_rate == "1:4":
sdram_clk = ClockSignal("sys4x_ps")
else:
sdram_clk = ClockSignal("sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
pll2 = ECP5PLL()
self.pll2 = pll2
pll2.register_clkin(clk48, 48e6)
pll2.create_clkout(self.cd_video, 25e6)
pll2.create_clkout(self.cd_video5x, 125e6)
self.cd_usb_12 = ClockDomain()
self.cd_usb = ClockDomain()
self.cd_usb_48 = ClockDomain()
self.cd_usb_48 = self.cd_usb
pll2.create_clkout(self.cd_usb, 48e6)
pll2.create_clkout(self.cd_usb_12, 12e6)
self.comb += pll2.reset.eq(~por_done)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v0", device="12F", sdram_device="W9825G6KH6", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_usb_host=False, **kwargs):
platform = machdyne_vanille.Platform(revision=revision, device=device ,toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
# SoCCore ----------------------------------------------------------------------------------
kwargs['uart_name'] = "stub"
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Vanille", **kwargs)
# DRAM -------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
if sdram_rate == "1:2":
sdrphy_cls = HalfRateGENSDRPHY
elif sdram_rate == "1:4":
from litedram.phy import QuarterRateGENSDRPHY
sdrphy_cls = QuarterRateGENSDRPHY
else:
sdrphy_cls = GENSDRPHY
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
if sdram_device == "W9825G6KH6":
self.add_sdram("sdram",
phy = self.sdrphy,
module = W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 0)
)
if sdram_device == "IS42S16320":
self.add_sdram("sdram",
phy = self.sdrphy,
module = IS42S16320(self.clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 0)
)
# USB Host ---------------------------------------------------------------------------------
if with_usb_host:
self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
# DDMI Framebuffer -------------------------------------------------------------------------------------
self.videophy = VideoHDMIPHY(platform.request("ddmi"),
clock_domain="video")
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz",
clock_domain="video", format="rgb565")
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_vanille.Platform, description="LiteX SoC on Vanille")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--revision", default="v0", help="Board Revision (v0).")
parser.add_argument("--device", default="12F", help="ECP5 device (25F, 45F or 85F).")
parser.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
parser.add_argument("--sdram-device", default="W9825G6KH6", help="SDRAM device (W9825G6KH6 or IS42S16320).")
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sys_clk_freq = int(float(args.sys_clk_freq)),
sdram_device = args.sdram_device,
with_usb_host = args.with_usb_host,
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer(cable=args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()

214
litex_boards/targets/machdyne_vivaldi_ml1.py Executable file
View File

@ -0,0 +1,214 @@
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
#
# SPDX-License-Identifier: BSD-2-Clause
#
import os
import sys
import json
from migen import *
from litex.gen import *
from litex_boards.platforms import machdyne_vivaldi_ml1
from litex.build.io import DDROutput
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock import *
from litex.soc.cores.usb_ohci import USBOHCI
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.interconnect.csr_eventmanager import *
from litedram.modules import W9825G6KH6
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litex.soc.integration.soc import SoCRegion
# CRG ---------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, sdram_rate):
self.rst = Signal()
self.cd_por = ClockDomain()
self.cd_sys = ClockDomain()
self.cd_init = ClockDomain()
self.cd_video = ClockDomain()
self.cd_video5x = ClockDomain()
self.cd_eth = ClockDomain()
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk48 = platform.request("clk48")
clk50 = platform.request("clk50")
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | self.rst)
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
self.cd_sys2x = ClockDomain()
self.cd_sys2x_ps = ClockDomain()
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
elif sdram_rate == "1:4":
self.cd_sys2x = ClockDomain()
self.cd_sys4x = ClockDomain()
self.cd_sys4x_ps = ClockDomain()
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_ps, 4*sys_clk_freq, phase=180)
else:
self.cd_sys_ps = ClockDomain()
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
if sdram_rate == "1:2":
sdram_clk = ClockSignal("sys2x_ps")
elif sdram_rate == "1:4":
sdram_clk = ClockSignal("sys4x_ps")
else:
sdram_clk = ClockSignal("sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
pll2 = ECP5PLL()
self.pll2 = pll2
pll2.register_clkin(clk50, 50e6)
pll2.create_clkout(self.cd_eth, 50e6)
pll2.create_clkout(self.cd_video, 25e6)
pll2.create_clkout(self.cd_video5x, 125e6)
self.comb += pll2.reset.eq(~por_done)
pll3 = ECP5PLL()
self.pll3 = pll3
pll3.register_clkin(clk48, 48e6)
self.cd_usb_12 = ClockDomain()
self.cd_usb = ClockDomain()
self.cd_usb_48 = ClockDomain()
self.cd_usb_48 = self.cd_usb
pll3.create_clkout(self.cd_usb, 48e6)
pll3.create_clkout(self.cd_usb_12, 12e6)
self.comb += pll3.reset.eq(~por_done)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"usb_ohci": 0xc0000000,
}}
def __init__(self, revision="v2", device="45F", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_usb_host=False, with_ethernet=False, **kwargs):
platform = machdyne_vivaldi_ml1.Platform(revision=revision, device=device ,toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Vivaldi ML1", **kwargs)
# DRAM -------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
if sdram_rate == "1:2":
sdrphy_cls = HalfRateGENSDRPHY
elif sdram_rate == "1:4":
sdrphy_cls = QuarterRateGENSDRPHY
else:
sdrphy_cls = GENSDRPHY
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# USB Host ---------------------------------------------------------------------------------
if with_usb_host:
self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
from liteeth.phy.rmii import LiteEthPHYRMII
self.ethphy = LiteEthPHYRMII(
clock_pads=None,
pads = platform.request("eth", 0),
with_hw_init_reset=True,
refclk_cd="eth")
self.add_csr("ethphy")
self.add_ethernet(name="ethmac", phy=self.ethphy,
phy_cd="ethphy_eth")
self.ethphy1 = LiteEthPHYRMII(
clock_pads=None,
pads = platform.request("eth", 1),
with_hw_init_reset=True,
refclk_cd="eth")
self.add_csr("ethphy1")
self.add_ethernet(name="ethmac1", phy=self.ethphy1,
phy_cd="ethphy1_eth")
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=machdyne_vivaldi_ml1.Platform, description="LiteX SoC on Vivaldi ML1")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--revision", default="v2", help="Board Revision (v0, v1, v2).")
parser.add_argument("--device", default="45F", help="ECP5 device (12F, 25F, 45F or 85F).")
parser.add_argument("--cable", default="dirtyJtag", help="Specify an openFPGALoader cable.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
parser.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_usb_host = args.with_usb_host,
with_ethernet = args.with_ethernet,
**parser.soc_argdict)
if args.with_sdcard:
soc.add_sdcard()
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer(cable=args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()