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targets/machdyne_vanille: set uart_name to stub

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inc 2024-06-22 12:13:30 +02:00
parent a1df389c7e
commit cb43cdf6f9
1 changed files with 3 additions and 0 deletions
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litex_boards/targets/machdyne_vanille.py
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@ -111,6 +111,9 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
# SoCCore ----------------------------------------------------------------------------------
kwargs['uart_name'] = "stub"
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Vanille", **kwargs)
# DRAM -------------------------------------------------------------------------------------