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Merge pull request #30 from mithro/fomu-update 

Updating the templates for Fomu.
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Tim Ansell 2020-01-03 08:40:18 +00:00 committed by GitHub
parent 2b43a18a3c 250706b98c
commit f8f2301a3e
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1 changed files with 28 additions and 10 deletions
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38
litex_boards/partner/targets/fomu.py
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@ -220,21 +220,39 @@ class BaseSoC(SoCCore):
if usb_bridge: if usb_bridge:
self.add_wb_master(self.usb.debug_bridge.wishbone) self.add_wb_master(self.usb.debug_bridge.wishbone)
# Override default LiteX's yosys/build templates
assert hasattr(platform.toolchain, "yosys_template")
assert hasattr(platform.toolchain, "build_template")
platform.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
platform.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command. # Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# "-reult" adds an additional LUT pass to pack more stuff in, and # The "-reult" adds an additional LUT pass to pack more stuff in,
# "-dffe_min_ce_use 4" flag prevents Yosys from generating a # and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops. # Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently. # This increases density, and lets us use the FPGA more efficiently.
#platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4" platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
platform.toolchain.yosys_template[2] += " -dsp"
# Allow us to set the nextpnr seed, because some values don't meet timing. # Disable final deep-sleep power down so firmware words are loaded
#platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed) # onto softcore's address bus.
platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
# Different placers can improve packing efficiency, however not all placers # Allow us to set the nextpnr seed
# are enabled on all builds of nextpnr-ice40. Let the user override which platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
# placer they want to use.
#if pnr_placer is not None: if placer is not None:
# platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(pnr_placer) platform.toolchain.build_template[1] += " --placer {}".format(placer)
class USBSoC(BaseSoC): class USBSoC(BaseSoC):