aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
This commit is contained in:
Florent Kermarrec
parent
fd1e655700
commit
f9619c4a8f
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@ -4,6 +4,7 @@
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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import sys
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from migen import *
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@ -47,21 +48,19 @@ class CRG(Module):
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# AllerSoC -----------------------------------------------------------------------------------------
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# PCIeSoC -----------------------------------------------------------------------------------------
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class AllerSoC(SoCSDRAM):
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class PCIeSoC(SoCSDRAM):
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SoCSDRAM.mem_map["csr"] = 0x80000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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def __init__(self, platform, with_pcie_uart=True):
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def __init__(self, platform, **kwargs):
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sys_clk_freq = int(100e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, sys_clk_freq,
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csr_data_width = 32,
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integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests
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ident = "Aller LiteX Test SoC", ident_version=True,
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with_uart=not with_pcie_uart)
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ident = "LiteX SoC on Tagus", ident_version=True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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@ -121,61 +120,6 @@ class AllerSoC(SoCSDRAM):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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# pcie_uart
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if with_pcie_uart:
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class PCIeUART(Module, AutoCSR):
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def __init__(self, uart):
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self.rx_valid = CSRStatus()
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self.rx_ready = CSR()
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self.rx_data = CSRStatus(8)
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self.tx_valid = CSR()
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self.tx_ready = CSRStatus()
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self.tx_data = CSRStorage(8)
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# # #
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# cpu to pcie
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self.comb += [
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self.rx_valid.status.eq(uart.sink.valid),
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uart.sink.ready.eq(self.rx_ready.re),
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self.rx_data.status.eq(uart.sink.data),
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]
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# pcie to cpu
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self.sync += [
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If(self.tx_valid.re,
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uart.source.valid.eq(1)
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).Elif(uart.source.ready,
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uart.source.valid.eq(0)
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)
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]
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self.comb += [
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self.tx_ready.status.eq(~uart.source.valid),
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uart.source.data.eq(self.tx_data.storage)
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]
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uart_interface = RS232PHYInterface()
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self.submodules.uart = UART(uart_interface)
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self.add_csr("uart")
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self.add_interrupt("uart")
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self.submodules.pcie_uart = PCIeUART(uart_interface)
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self.add_csr("pcie_uart")
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# Leds -------------------------------------------------------------------------------------
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# led blinking (sys)
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sys_counter = Signal(32)
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self.sync.sys += sys_counter.eq(sys_counter + 1)
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pcie_counter = Signal(32)
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self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
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self.comb += [
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platform.request("user_led", 0).eq(~self.pcie_phy._lnk_up.status),
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platform.request("user_led", 1).eq(~pcie_counter[26]),
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platform.request("user_led", 2).eq(~sys_counter[26]),
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]
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def generate_software_header(self, filename):
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csr_header = get_csr_header(self.csr_regions,
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self.constants,
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@ -186,13 +130,19 @@ class AllerSoC(SoCSDRAM):
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# Build --------------------------------------------------------------------------------------------
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def main():
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platform = aller.Platform()
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soc = AllerSoC(platform)
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builder = Builder(soc, output_dir="aller", csr_csv="aller/csr.csv",
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compile_gateware=not "no-compile" in sys.argv[1:])
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vns = builder.build(build_name="aller")
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soc.generate_software_header("aller/csr.h")
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parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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args.uart_name = "crossover"
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args.csr_data_width = 32
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platform = aller.Platform()
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soc = PCIeSoC(platform, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build()
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soc.generate_software_header("csr.h")
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if __name__ == "__main__":
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main()
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@ -4,6 +4,7 @@
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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import sys
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from migen import *
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@ -18,7 +19,6 @@ from litex.soc.cores.uart import *
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from litex.soc.integration.cpu_interface import get_csr_header
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from litedram.modules import MT8KTF51264
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from litedram.modules import _TechnologyTimings, _SpeedgradeTimings
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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@ -39,29 +39,27 @@ class CRG(Module):
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clk100 = platform.request("clk100")
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# NereidSoC ----------------------------------------------------------------------------------------
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# PCIeSoC -----------------------------------------------------------------------------------------
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class NereidSoC(SoCSDRAM):
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class PCIeSoC(SoCSDRAM):
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SoCSDRAM.mem_map["csr"] = 0x80000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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def __init__(self, platform, with_pcie_uart=True):
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def __init__(self, platform, **kwargs):
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sys_clk_freq = int(100e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, sys_clk_freq,
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csr_data_width = 32,
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integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests
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ident = "Nereid LiteX Test SoC", ident_version=True,
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with_uart = not with_pcie_uart)
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ident = "LiteX SoC on Nereid", ident_version=True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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@ -121,58 +119,6 @@ class NereidSoC(SoCSDRAM):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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# pcie uart
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if with_pcie_uart:
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class PCIeUART(Module, AutoCSR):
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def __init__(self, uart):
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self.rx_valid = CSRStatus()
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self.rx_ready = CSR()
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self.rx_data = CSRStatus(8)
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self.tx_valid = CSR()
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self.tx_ready = CSRStatus()
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self.tx_data = CSRStorage(8)
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# # #
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# cpu to pcie
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self.comb += [
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self.rx_valid.status.eq(uart.sink.valid),
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uart.sink.ready.eq(self.rx_ready.re),
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self.rx_data.status.eq(uart.sink.data),
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]
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# pcie to cpu
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self.sync += [
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If(self.tx_valid.re,
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uart.source.valid.eq(1)
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).Elif(uart.source.ready,
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uart.source.valid.eq(0)
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)
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]
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self.comb += [
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self.tx_ready.status.eq(~uart.source.valid),
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uart.source.data.eq(self.tx_data.storage)
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]
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uart_interface = RS232PHYInterface()
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self.submodules.uart = UART(uart_interface)
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self.add_csr("uart")
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self.add_interrupt("uart")
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self.submodules.pcie_uart = PCIeUART(uart_interface)
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self.add_csr("pcie_uart")
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# Leds -------------------------------------------------------------------------------------
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# led blinking (sys)
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sys_counter = Signal(32)
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self.sync.sys += sys_counter.eq(sys_counter + 1)
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rgb = platform.request("rgb_led")
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self.comb += [
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rgb.r.eq(1),
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rgb.g.eq(sys_counter[26]),
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rgb.b.eq(1),
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]
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def generate_software_header(self, filename):
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csr_header = get_csr_header(self.csr_regions,
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self.constants,
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@ -183,13 +129,19 @@ class NereidSoC(SoCSDRAM):
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# Build --------------------------------------------------------------------------------------------
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def main():
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platform = nereid.Platform()
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soc = NereidSoC(platform)
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builder = Builder(soc, output_dir="nereid", csr_csv="nereid/csr.csv",
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compile_gateware=not "no-compile" in sys.argv[1:])
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vns = builder.build(build_name="nereid")
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soc.generate_software_header("nereid/csr.h")
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parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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args.uart_name = "crossover"
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args.csr_data_width = 32
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platform = nereid.Platform()
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soc = PCIeSoC(platform, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build()
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soc.generate_software_header("csr.h")
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if __name__ == "__main__":
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main()
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@ -2,9 +2,9 @@
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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import sys
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from migen import *
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@ -40,30 +40,28 @@ class CRG(Module):
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clk100 = platform.request("clk100")
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(platform.request("rst"))
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.comb += pll.reset.eq(platform.request("rst"))
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# TagusSoC -----------------------------------------------------------------------------------------
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# PCIeSoC -----------------------------------------------------------------------------------------
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class TagusSoC(SoCSDRAM):
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class PCIeSoC(SoCSDRAM):
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SoCSDRAM.mem_map["csr"] = 0x80000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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def __init__(self, platform, with_pcie_uart=True):
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def __init__(self, platform, **kwargs):
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sys_clk_freq = int(100e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, sys_clk_freq,
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csr_data_width = 32,
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integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests
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ident = "Tagus LiteX Test SoC", ident_version=True,
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with_uart = not with_pcie_uart)
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ident = "LiteX SoC on Tagus", ident_version=True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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@ -87,8 +85,8 @@ class TagusSoC(SoCSDRAM):
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self.add_csr("ddrphy")
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sdram_module = MT41J128M16(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# PCIe -------------------------------------------------------------------------------------
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# pcie phy
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@ -123,57 +121,6 @@ class TagusSoC(SoCSDRAM):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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# pcie_uart
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if with_pcie_uart:
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class PCIeUART(Module, AutoCSR):
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def __init__(self, uart):
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self.rx_valid = CSRStatus()
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self.rx_ready = CSR()
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self.rx_data = CSRStatus(8)
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self.tx_valid = CSR()
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self.tx_ready = CSRStatus()
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self.tx_data = CSRStorage(8)
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# # #
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# cpu to pcie
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self.comb += [
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self.rx_valid.status.eq(uart.sink.valid),
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uart.sink.ready.eq(self.rx_ready.re),
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self.rx_data.status.eq(uart.sink.data),
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]
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# pcie to cpu
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self.sync += [
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If(self.tx_valid.re,
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uart.source.valid.eq(1)
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).Elif(uart.source.ready,
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uart.source.valid.eq(0)
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)
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]
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self.comb += [
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self.tx_ready.status.eq(~uart.source.valid),
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uart.source.data.eq(self.tx_data.storage)
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]
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uart_interface = RS232PHYInterface()
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self.submodules.uart = UART(uart_interface)
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self.add_csr("uart")
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self.add_interrupt("uart")
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self.submodules.pcie_uart = PCIeUART(uart_interface)
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self.add_csr("pcie_uart")
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# Leds -------------------------------------------------------------------------------------
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# led blinking (sys)
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sys_counter = Signal(32)
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self.sync.sys += sys_counter.eq(sys_counter + 1)
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self.comb += [
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platform.request("user_led", 0).eq(1),
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platform.request("user_led", 1).eq(sys_counter[26]),
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platform.request("user_led", 2).eq(1),
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]
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def generate_software_header(self, filename):
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csr_header = get_csr_header(self.csr_regions,
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self.constants,
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@ -184,13 +131,19 @@ class TagusSoC(SoCSDRAM):
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# Build --------------------------------------------------------------------------------------------
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def main():
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platform = tagus.Platform()
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soc = TagusSoC(platform)
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builder = Builder(soc, output_dir="tagus", csr_csv="tagus/csr.csv",
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compile_gateware=not "no-compile" in sys.argv[1:])
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vns = builder.build(build_name="tagus")
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soc.generate_software_header("tagus/csr.h")
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parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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args.uart_name = "crossover"
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args.csr_data_width = 32
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platform = tagus.Platform()
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soc = PCIeSoC(platform, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build()
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soc.generate_software_header("csr.h")
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if __name__ == "__main__":
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main()
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