Merge pull request #259 from danc86/clnexevn-unreserve-spi-flash-pins
lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL
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fb9bb17835
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@ -69,7 +69,6 @@ class BaseSoC(SoCCore):
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}
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def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG400C", toolchain="radiant", with_led_chaser=True, **kwargs):
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platform = crosslink_nx_evn.Platform(device=device, toolchain=toolchain)
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platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
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# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
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kwargs["integrated_sram_size"] = 0
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