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targets/pcie: make pcie optional (--with-pcie) and avoid forcing uart to crossover.

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This commit is contained in:
Florent Kermarrec 2020-06-30 18:44:00 +02:00
parent 7a48a61605
commit fe3ea805bc
4 changed files with 158 additions and 179 deletions

94
litex_boards/targets/acorn_cle_215.py
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@ -5,8 +5,7 @@
# Build/Use ---------------------------------------------------------------------------------------- # Build/Use ----------------------------------------------------------------------------------------
# Build/Load bitstream: # Build/Load bitstream:
# ./acorn_cle_215.py --build --driver # ./acorn_cle_215.py --uart-name=crossover --with-pcie --build --driver --load (or --flash)
# ./acorn_cle_215.py --load (or --flash)
# #
#.Build the kernel and load it: #.Build the kernel and load it:
# cd build/<platform>/driver/kernel # cd build/<platform>/driver/kernel
@ -71,7 +70,7 @@ class CRG(Module):
# BaseSoC ----------------------------------------------------------------------------------------- # BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs): def __init__(self, platform, with_pcie=False, **kwargs):
sys_clk_freq = int(100e6) sys_clk_freq = int(100e6)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -103,50 +102,51 @@ class BaseSoC(SoCCore):
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# PHY if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), # PHY
data_width = 128, self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
bar0_size = 0x20000) data_width = 128,
self.pcie_phy.add_timing_constraints(platform) bar0_size = 0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.pcie_phy.add_timing_constraints(platform)
self.add_csr("pcie_phy") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.comb += platform.request("pcie_clkreq_n").eq(0) self.add_csr("pcie_phy")
self.comb += platform.request("pcie_clkreq_n").eq(0)
# Endpoint # Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
# Wishbone bridge # Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
base_address = self.mem_map["csr"]) base_address = self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone) self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 # DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024, with_buffering = True, buffering_depth=1024,
with_loopback = True) with_loopback = True)
self.add_csr("pcie_dma0") self.add_csr("pcie_dma0")
# DMA1 # DMA1
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024, with_buffering = True, buffering_depth=1024,
with_loopback = True) with_loopback = True)
self.add_csr("pcie_dma1") self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2) self.add_constant("DMA_CHANNELS", 2)
# MSI # MSI
self.submodules.pcie_msi = LitePCIeMSI() self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi") self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = { self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
} }
for i, (k, v) in enumerate(sorted(self.interrupts.items())): for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v) self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i) self.add_constant(k + "_INTERRUPT", i)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
@ -158,20 +158,20 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+") parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
parser.add_argument("--flash", action="store_true", help="Flash bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments # Enforce arguments
args.uart_name = "crossover"
args.csr_data_width = 32 args.csr_data_width = 32
platform = acorn_cle_215.Platform() platform = acorn_cle_215.Platform()
soc = BaseSoC(platform, **soc_sdram_argdict(args)) soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)

81
litex_boards/targets/aller.py
View file

@ -54,7 +54,7 @@ class CRG(Module):
# BaseSoC ----------------------------------------------------------------------------------------- # BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs): def __init__(self, platform, with_pcie=False, **kwargs):
sys_clk_freq = int(100e6) sys_clk_freq = int(100e6)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -86,49 +86,42 @@ class BaseSoC(SoCCore):
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# PHY if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), # PHY
data_width = 128, self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
bar0_size = 0x20000) data_width = 128,
self.pcie_phy.add_timing_constraints(platform) bar0_size = 0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.pcie_phy.add_timing_constraints(platform)
self.add_csr("pcie_phy") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint # Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
# Wishbone bridge # Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
base_address = self.mem_map["csr"]) base_address = self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone) self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 # DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024, with_buffering = True, buffering_depth=1024,
with_loopback = True) with_loopback = True)
self.add_csr("pcie_dma0") self.add_csr("pcie_dma0")
# DMA1 self.add_constant("DMA_CHANNELS", 1)
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024,
with_loopback = True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2) # MSI
self.submodules.pcie_msi = LitePCIeMSI()
# MSI self.add_csr("pcie_msi")
self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.add_csr("pcie_msi") self.interrupts = {
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
self.interrupts = { "PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, }
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq, for i, (k, v) in enumerate(sorted(self.interrupts.items())):
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, self.comb += self.pcie_msi.irqs[i].eq(v)
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq, self.add_constant(k + "_INTERRUPT", i)
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
@ -140,19 +133,19 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Aller") parser = argparse.ArgumentParser(description="LiteX SoC on Aller")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments # Enforce arguments
args.uart_name = "crossover"
args.csr_data_width = 32 args.csr_data_width = 32
platform = aller.Platform() platform = aller.Platform()
soc = BaseSoC(platform, **soc_sdram_argdict(args)) soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)

81
litex_boards/targets/nereid.py
View file

@ -51,7 +51,7 @@ class CRG(Module):
# BaseSoC ----------------------------------------------------------------------------------------- # BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs): def __init__(self, platform, with_pcie=False, **kwargs):
sys_clk_freq = int(100e6) sys_clk_freq = int(100e6)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -83,67 +83,60 @@ class BaseSoC(SoCCore):
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# PHY if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), # PHY
data_width = 128, self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
bar0_size = 0x20000) data_width = 128,
self.pcie_phy.add_timing_constraints(platform) bar0_size = 0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.pcie_phy.add_timing_constraints(platform)
self.add_csr("pcie_phy") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint # Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
# Wishbone bridge # Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
base_address = self.mem_map["csr"]) base_address = self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone) self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 # DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024, with_buffering = True, buffering_depth=1024,
with_loopback = True) with_loopback = True)
self.add_csr("pcie_dma0") self.add_csr("pcie_dma0")
# DMA1 self.add_constant("DMA_CHANNELS", 1)
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024,
with_loopback = True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2) # MSI
self.submodules.pcie_msi = LitePCIeMSI()
# MSI self.add_csr("pcie_msi")
self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.add_csr("pcie_msi") self.interrupts = {
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
self.interrupts = { "PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, }
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq, for i, (k, v) in enumerate(sorted(self.interrupts.items())):
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, self.comb += self.pcie_msi.irqs[i].eq(v)
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq, self.add_constant(k + "_INTERRUPT", i)
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nereid") parser = argparse.ArgumentParser(description="LiteX SoC on Nereid")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments # Enforce arguments
args.uart_name = "crossover"
args.csr_data_width = 32 args.csr_data_width = 32
platform = nereid.Platform() platform = nereid.Platform()
soc = BaseSoC(platform, **soc_sdram_argdict(args)) soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)

81
litex_boards/targets/tagus.py
View file

@ -54,7 +54,7 @@ class CRG(Module):
# BaseSoC ----------------------------------------------------------------------------------------- # BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs): def __init__(self, platform, with_pcie=False, **kwargs):
sys_clk_freq = int(100e6) sys_clk_freq = int(100e6)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -86,49 +86,42 @@ class BaseSoC(SoCCore):
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# PHY if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), # PHY
data_width = 64, self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
bar0_size = 0x20000) data_width = 64,
self.pcie_phy.add_timing_constraints(platform) bar0_size = 0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.pcie_phy.add_timing_constraints(platform)
self.add_csr("pcie_phy") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint # Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# Wishbone bridge # Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
base_address = self.mem_map["csr"]) base_address = self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone) self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 # DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024, with_buffering = True, buffering_depth=1024,
with_loopback = True) with_loopback = True)
self.add_csr("pcie_dma0") self.add_csr("pcie_dma0")
# DMA1 self.add_constant("DMA_CHANNELS", 1)
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024,
with_loopback = True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2) # MSI
self.submodules.pcie_msi = LitePCIeMSI()
# MSI self.add_csr("pcie_msi")
self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.add_csr("pcie_msi") self.interrupts = {
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
self.interrupts = { "PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, }
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq, for i, (k, v) in enumerate(sorted(self.interrupts.items())):
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, self.comb += self.pcie_msi.irqs[i].eq(v)
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq, self.add_constant(k + "_INTERRUPT", i)
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
@ -140,19 +133,19 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Tagus") parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments # Enforce arguments
args.uart_name = "crossover"
args.csr_data_width = 32 args.csr_data_width = 32
platform = tagus.Platform() platform = tagus.Platform()
soc = BaseSoC(platform, **soc_sdram_argdict(args)) soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)