mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
targets/pcie: make pcie optional (--with-pcie) and avoid forcing uart to crossover.
This commit is contained in:
Florent Kermarrec
parent
7a48a61605
commit
fe3ea805bc
4 changed files with 158 additions and 179 deletions
litex_boards/targets
|
|
@ -5,8 +5,7 @@
|
|||
|
||||
# Build/Use ----------------------------------------------------------------------------------------
|
||||
# Build/Load bitstream:
|
||||
# ./acorn_cle_215.py --build --driver
|
||||
# ./acorn_cle_215.py --load (or --flash)
|
||||
# ./acorn_cle_215.py --uart-name=crossover --with-pcie --build --driver --load (or --flash)
|
||||
#
|
||||
#.Build the kernel and load it:
|
||||
# cd build/<platform>/driver/kernel
|
||||
|
|
@ -71,7 +70,7 @@ class CRG(Module):
|
|||
# BaseSoC -----------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, platform, **kwargs):
|
||||
def __init__(self, platform, with_pcie=False, **kwargs):
|
||||
sys_clk_freq = int(100e6)
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
|
|
@ -103,6 +102,7 @@ class BaseSoC(SoCCore):
|
|||
)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
# PHY
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
|
|
@ -159,7 +159,8 @@ class BaseSoC(SoCCore):
|
|||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
|
||||
builder_args(parser)
|
||||
|
|
@ -167,11 +168,10 @@ def main():
|
|||
args = parser.parse_args()
|
||||
|
||||
# Enforce arguments
|
||||
args.uart_name = "crossover"
|
||||
args.csr_data_width = 32
|
||||
|
||||
platform = acorn_cle_215.Platform()
|
||||
soc = BaseSoC(platform, **soc_sdram_argdict(args))
|
||||
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(run=args.build)
|
||||
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ class CRG(Module):
|
|||
# BaseSoC -----------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, platform, **kwargs):
|
||||
def __init__(self, platform, with_pcie=False, **kwargs):
|
||||
sys_clk_freq = int(100e6)
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
|
|
@ -86,6 +86,7 @@ class BaseSoC(SoCCore):
|
|||
)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
# PHY
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
|
|
@ -108,13 +109,7 @@ class BaseSoC(SoCCore):
|
|||
with_loopback = True)
|
||||
self.add_csr("pcie_dma0")
|
||||
|
||||
# DMA1
|
||||
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma1")
|
||||
|
||||
self.add_constant("DMA_CHANNELS", 2)
|
||||
self.add_constant("DMA_CHANNELS", 1)
|
||||
|
||||
# MSI
|
||||
self.submodules.pcie_msi = LitePCIeMSI()
|
||||
|
|
@ -123,8 +118,6 @@ class BaseSoC(SoCCore):
|
|||
self.interrupts = {
|
||||
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
|
||||
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
|
||||
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
|
||||
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
|
||||
}
|
||||
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
|
||||
self.comb += self.pcie_msi.irqs[i].eq(v)
|
||||
|
|
@ -141,6 +134,7 @@ class BaseSoC(SoCCore):
|
|||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX SoC on Aller")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||
builder_args(parser)
|
||||
|
|
@ -148,11 +142,10 @@ def main():
|
|||
args = parser.parse_args()
|
||||
|
||||
# Enforce arguments
|
||||
args.uart_name = "crossover"
|
||||
args.csr_data_width = 32
|
||||
|
||||
platform = aller.Platform()
|
||||
soc = BaseSoC(platform, **soc_sdram_argdict(args))
|
||||
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(run=args.build)
|
||||
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ class CRG(Module):
|
|||
# BaseSoC -----------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, platform, **kwargs):
|
||||
def __init__(self, platform, with_pcie=False, **kwargs):
|
||||
sys_clk_freq = int(100e6)
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
|
|
@ -83,6 +83,7 @@ class BaseSoC(SoCCore):
|
|||
)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
# PHY
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
|
|
@ -105,13 +106,7 @@ class BaseSoC(SoCCore):
|
|||
with_loopback = True)
|
||||
self.add_csr("pcie_dma0")
|
||||
|
||||
# DMA1
|
||||
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma1")
|
||||
|
||||
self.add_constant("DMA_CHANNELS", 2)
|
||||
self.add_constant("DMA_CHANNELS", 1)
|
||||
|
||||
# MSI
|
||||
self.submodules.pcie_msi = LitePCIeMSI()
|
||||
|
|
@ -120,8 +115,6 @@ class BaseSoC(SoCCore):
|
|||
self.interrupts = {
|
||||
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
|
||||
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
|
||||
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
|
||||
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
|
||||
}
|
||||
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
|
||||
self.comb += self.pcie_msi.irqs[i].eq(v)
|
||||
|
|
@ -132,6 +125,7 @@ class BaseSoC(SoCCore):
|
|||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX SoC on Nereid")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||
builder_args(parser)
|
||||
|
|
@ -139,11 +133,10 @@ def main():
|
|||
args = parser.parse_args()
|
||||
|
||||
# Enforce arguments
|
||||
args.uart_name = "crossover"
|
||||
args.csr_data_width = 32
|
||||
|
||||
platform = nereid.Platform()
|
||||
soc = BaseSoC(platform, **soc_sdram_argdict(args))
|
||||
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(run=args.build)
|
||||
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ class CRG(Module):
|
|||
# BaseSoC -----------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, platform, **kwargs):
|
||||
def __init__(self, platform, with_pcie=False, **kwargs):
|
||||
sys_clk_freq = int(100e6)
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
|
|
@ -86,6 +86,7 @@ class BaseSoC(SoCCore):
|
|||
)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
# PHY
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
|
||||
data_width = 64,
|
||||
|
|
@ -108,13 +109,7 @@ class BaseSoC(SoCCore):
|
|||
with_loopback = True)
|
||||
self.add_csr("pcie_dma0")
|
||||
|
||||
# DMA1
|
||||
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma1")
|
||||
|
||||
self.add_constant("DMA_CHANNELS", 2)
|
||||
self.add_constant("DMA_CHANNELS", 1)
|
||||
|
||||
# MSI
|
||||
self.submodules.pcie_msi = LitePCIeMSI()
|
||||
|
|
@ -123,8 +118,6 @@ class BaseSoC(SoCCore):
|
|||
self.interrupts = {
|
||||
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
|
||||
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
|
||||
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
|
||||
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
|
||||
}
|
||||
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
|
||||
self.comb += self.pcie_msi.irqs[i].eq(v)
|
||||
|
|
@ -141,6 +134,7 @@ class BaseSoC(SoCCore):
|
|||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||
builder_args(parser)
|
||||
|
|
@ -148,11 +142,10 @@ def main():
|
|||
args = parser.parse_args()
|
||||
|
||||
# Enforce arguments
|
||||
args.uart_name = "crossover"
|
||||
args.csr_data_width = 32
|
||||
|
||||
platform = tagus.Platform()
|
||||
soc = BaseSoC(platform, **soc_sdram_argdict(args))
|
||||
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(run=args.build)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue