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1030 commits 9 branches 14 tags 12 MiB
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2 commits

Author SHA1 Message Date
alainlou
1333f89ed6 rz_easyfpga: adjust SDRAM clk phase 
- also add 1:2 rate
 2021-09-22 00:26:28 -04:00
Alain Lou
610e82d774
Add initial RZ-EasyFPGA support! (#270) 2021-09-21 09:55:22 +02:00