9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
496b2cfab9
targets/gowin: Switch to get_bitstream_filename.
2022-03-17 09:40:10 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
2df7fd573c
Update sipeed_tang_nano_9k.py
...
Add Gowin programmer support
2022-03-08 14:04:28 +08:00
4c9bc53a3c
add Win/powershell and WSL support
2022-03-08 13:24:56 +08:00
a19c03fa55
targets: Switch to generic/portable HyperRAM core from LiteX.
2022-03-01 09:10:19 +01:00
cc1b46f106
tang_nano_9k: Fix HyperRAM integration.
2022-01-24 18:35:12 +01:00
f533e7f8ba
sipeed_tang_nano_9k: enable copackaged PSRAM
...
Also enable SPI SDCard which was pending by the lack of main_ram
previously.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-23 03:37:03 +08:00
e699c377a5
sipeed_tang_nano_9k: new board
...
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-22 11:45:49 +08:00
Florent Kermarrec
curliph
Icenowy Zheng